Patents Examined by Tsz K. Chiu
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Patent number: 11715684Abstract: A semiconductor device includes lower circuit patterns on a lower substrate; lower bonding patterns on the lower circuit patterns, the lower bonding patterns including a conductive material and being electrically connected to the lower circuit patterns; upper bonding patterns on and contacting the lower bonding patterns, and including a conductive material; a passive device on the upper bonding patterns, and including a conductive material and contacting one of the upper bonding patterns; a gate electrode structure on the passive device, and including gate electrodes spaced apart from each other in a first direction, each of which extends in a second direction, and extension lengths in the second direction of the gate electrodes increasing from a lowermost level toward an uppermost level in a stepwise manner; a channel extending through at least a portion of the gate electrode structure; and an upper substrate on the channel.Type: GrantFiled: July 15, 2021Date of Patent: August 1, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sungmin Hwang, Jiwon Kim, Jaeho Ahn, Joonsung Lim, Sukkang Sung
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Patent number: 11715785Abstract: A semiconductor device includes a gate structure located on a substrate; and a raised source/drain region adjacent to the gate structure. An interface is between the gate structure and the substrate. The raised source/drain region includes a stressor layer providing strain to a channel under the gate structure; and a silicide layer in the stressor layer. The silicide layer extends from a top surface of the raised source/drain region and ends below the interface by a predetermined depth. The predetermined depth allows the stressor layer to maintain the strain of the channel.Type: GrantFiled: April 22, 2021Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shin-Jiun Kuang, Yi-Han Wang, Tsung-Hsing Yu, Yi-Ming Sheu
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Patent number: 11716847Abstract: A semiconductor device is provided. The semiconductor device includes word line layers and insulating layers that are alternatingly stacked along a vertical direction perpendicular to a substrate of the semiconductor device. The semiconductor device includes a channel structure that extends along the vertical direction through the word line layers and the insulating layers. A cross-section of the channel structure that is perpendicular to the vertical axis includes channel layer sections that are spaced apart from one another.Type: GrantFiled: December 7, 2020Date of Patent: August 1, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Tingting Gao, Lei Xue, Xiaoxin Liu, Wanbo Geng
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Patent number: 11713241Abstract: The present disclosure provides a packaging method, including: providing a first semiconductor substrate; forming a bonding region on the first semiconductor substrate, wherein the bonding region of the first semiconductor substrate includes a first bonding metal layer and a second bonding metal layer; providing a second semiconductor substrate having a bonding region, wherein the bonding region of the second semiconductor substrate includes a third bonding layer; and bonding the first semiconductor substrate to the second semiconductor substrate by bringing the bonding region of the first semiconductor substrate in contact with the bonding region of the second semiconductor substrate; wherein the first and third bonding metal layers include copper (Cu), and the second bonding metal layer includes Tin (Sn). An associated packaging structure is also disclosed.Type: GrantFiled: August 2, 2021Date of Patent: August 1, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chih-Ming Chen, Yuan-Chih Hsieh, Chung-Yi Yu
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Patent number: 11711919Abstract: A semiconductor memory device comprises: a plurality of first conductive layers arranged separated from each other in a first direction; a plurality of second conductive layers arranged, electrically insulated from the plurality of first conductive layers, at a different position in a second direction intersecting the first direction with respect to the first conductive layers; a plurality of memory structures; and a source structure. Respective one ends of the plurality of memory structures and one end of the source structure are electrically connected. The respective other ends of the plurality of memory structures are respectively electrically connected to different first wirings of a plurality of first wirings formed in the same layer in the first direction. The other end of the source structure is electrically connected to a second wiring formed in a different layer from the plurality of first wirings in the first direction.Type: GrantFiled: September 14, 2020Date of Patent: July 25, 2023Assignee: Kioxia CorporationInventor: Daigo Ichinose
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Patent number: 11669213Abstract: An organic electroluminescent device with a touch sensor including: a first substrate; a second substrate arranged opposite to the first substrate; an organic EL element layer arranged above the first substrate; a first scaling film arranged toward the second substrate of the organic EL element layer, covering the organic EL element layer, and including a first inorganic layer; plural first detection electrodes extending in one direction, and arranged in parallel toward the second substrate of the first sealing film; a second sealing film arranged toward the second substrate of the first detection electrodes, and including a second inorganic layer; plural second detection electrodes extending in another direction different from the one direction, and arranged in parallel toward the second substrate of the second sealing film; and a touch sensor control unit controlling a potential to detect a touch with a display surface.Type: GrantFiled: September 30, 2020Date of Patent: June 6, 2023Assignee: Japan Display Inc.Inventors: Toshihiro Sato, Ryoichi Ito
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Patent number: 11672119Abstract: A vertical memory device includes a gate electrode structure, channels, a charge storage structure, and a division pattern. The gate electrode includes gate electrodes spaced apart from each other in a first direction. The channel extends through the gate electrode structure, and includes a first portion and a second portion on and contacting the first portion. The second portion includes a lower surface having a width less than that of an upper surface of the first portion. The charge storage structure covers an outer sidewall of the channel. The division pattern extends between the channels in a second direction, and includes a first dummy channel and a first dummy charge storage structure covering a sidewall and a lower surface thereof. The first dummy channel includes the same material as that the channel, and the first dummy charge storage structure includes the same material as the charge storage structure.Type: GrantFiled: September 22, 2020Date of Patent: June 6, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jisung Cheon, Jiye Noh, Byunggon Park, Jinsoo Lim
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Patent number: 11658155Abstract: A semiconductor storage device includes a substrate, a plurality of conductive layers arranged in a first direction intersecting a surface of the substrate, and a semiconductor layer extending in the first direction and penetrating the plurality of conductive layers. The plurality of conductive layers includes a first conductive layer and a second conductive layer that are adjacent to each other, a third conductive layer and a fourth conductive layer that are adjacent to each other, and a fifth conductive layer and a sixth conductive layer that are adjacent to each other.Type: GrantFiled: August 31, 2020Date of Patent: May 23, 2023Assignee: KIOXIA CORPORATIONInventors: Masashi Yamaoka, Kazuhiro Tomishige, Naoki Yamamoto
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Patent number: 11653556Abstract: A flex-tolerant structure includes a flexible and foldable substrate and traces on the substrate. Each trace includes a stretch-resistant layer and a metal layer covering the stretch-resistant layer, electrical flow can persist through these layers even if the traces are fractured. A display panel is also disclosed.Type: GrantFiled: April 9, 2020Date of Patent: May 16, 2023Assignees: Interface Technology (ChengDu) Co, Ltd., INTERFACE OPTOELECTRONICS (SHENZHEN) CO, LTD., GENERAL INTERFACE SOLUTION LIMITEDInventor: Po-Ching Lin
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Patent number: 11631692Abstract: A semiconductor memory device includes a peripheral logic structure including peripheral circuits on a substrate, a horizontal semiconductor layer extending along a top surface of the peripheral logic structure, a plurality of stack structures arranged on the horizontal semiconductor layer along a first direction, and a plurality of electrode separation regions in each of the plurality of stack structures to extend in a second direction, which is different from the first direction, wherein each of the plurality of stack structures includes a first electrode pad and a second electrode pad on the first electrode pad, the first electrode pad protruding in the first direction beyond the second electrode pad by a first width, and the first electrode pad protrudes in the second direction beyond the second electrode pad by a second width, which is different from the first width.Type: GrantFiled: July 22, 2020Date of Patent: April 18, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hae Min Lee, Shin Hwan Kang, Jee Hoon Han
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Patent number: 11631783Abstract: In an embodiment a radiation-emitting semiconductor chip includes a semiconductor body having an active region configured to generate radiation, a first contact layer having a first contact area for external electrical contacting the radiation-emitting semiconductor chip and a first contact finger structure connected to the first contact area, a second contact layer having a second contact area for external electrical contacting the radiation-emitting semiconductor chip and a second contact finger structure connected to the second contact area, wherein the first contact finger structure and the second contact finger structure overlap in places in plan view of the radiation-emitting semiconductor chip, a current distribution layer electrically conductively connected to the first contact layer, a connection layer electrically conductively connected to the first contact layer via the current distribution layer and an insulation layer containing a dielectric material, wherein the insulation layer is arranged in pType: GrantFiled: September 21, 2021Date of Patent: April 18, 2023Assignee: OSRAM OLED GMBHInventors: Fabian Kopp, Attila Molnar, Bjoern Muermann, Franz Eberhard
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Patent number: 11631791Abstract: A semiconductor light-emitting device includes: a package substrate having a mounting surface on which a first circuit pattern and a second circuit pattern are disposed; a semiconductor LED chip mounted on the mounting surface, having a first surface which faces the mounting surface and on which a first electrode and a second electrode are disposed, a second surface opposing the first surface, and side surfaces located between the first surface and the second surface, the first electrode and the second electrode being connected to the first circuit pattern and the second circuit pattern, respectively; a wavelength conversion film disposed on the second surface; and a side surface inclined portion disposed on the side surfaces of the semiconductor LED chip, providing inclined surfaces, and including a light-transmitting resin containing a wavelength conversion material.Type: GrantFiled: March 29, 2021Date of Patent: April 18, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mi Jeong Yun, Jong Sup Song
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Patent number: 11616074Abstract: The present disclosure provides a semiconductor device comprising: a block separator including a semiconductor film and a multi-layered insulating film, wherein the multi-layered insulating film surrounds the semiconductor film; memory block stacks divided from each other by the block separator, each memory block stack including interlayer insulating films and conductive patterns alternately stacked, wherein the conductive patterns are coupled to memory cells; and channel structures passing through the memory block stacks and electrically coupled to the memory cells.Type: GrantFiled: April 27, 2020Date of Patent: March 28, 2023Assignee: SK hynix Inc.Inventor: Nam Jae Lee
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Patent number: 11610823Abstract: A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.Type: GrantFiled: November 4, 2019Date of Patent: March 21, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tong-Min Weng, Tsung-Han Wu
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Patent number: 11605680Abstract: A display device includes: a substrate having thereon a first subpixel, a second subpixel, and a third subpixel; a first electrode in each of the first to third subpixels on the substrate; a first bank between the first electrodes; a second bank on the first bank and having a width less than that of the first bank; a light emitting layer on the first electrodes, the first bank, and the second bank; and a second electrode on the light emitting layer. The light emitting layer provided on the second bank and the light emitting layer provided on the first bank are spaced apart from each other.Type: GrantFiled: September 25, 2019Date of Patent: March 14, 2023Assignee: LG Display Co., Ltd.Inventors: YuCheol Yang, Suhyeon Kim
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Patent number: 11594482Abstract: An integrated multilayer structure, includes a substrate film having a first side and an opposite second side. The substrate film includes electrically substantially insulating material, a circuit design including a number of electrically conductive areas of electrically conductive material on the first and/or second sides of the substrate film, and a connector including a number of electrically conductive contact elements. The connector is provided to the substrate film so that it extends to both the first and second sides of the substrate film and the number of electrically conductive contact elements connect to one or more of the conductive areas of the circuit design while being further configured to electrically couple to an external connecting element responsive to mating the external connecting element with the connector on the first or second side of or adjacent to the substrate film.Type: GrantFiled: July 6, 2021Date of Patent: February 28, 2023Assignee: TACTOTEK OYInventors: Jarmo Sääski, Mikko Heikkinen, Tero Heikkinen, Mika Paani, Jan Tillonen, Ronald Haag
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Patent number: 11563156Abstract: Light emitting devices and components having excellent chemical resistance and related methods are disclosed. In one embodiment, a component of a light emitting device can include a silver (Ag) portion, which can be silver on a substrate, and a protective layer disposed over the Ag portion. The protective layer can at least partially include an inorganic material for increasing the chemical resistance of the Ag portion.Type: GrantFiled: January 31, 2019Date of Patent: January 24, 2023Assignee: CreeLED, Inc.Inventors: Shaow B. Lin, James Sievert, Jesse Colin Reiherzer, Barry Rayfield, Christopher P. Hussell
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Patent number: 11562957Abstract: A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.Type: GrantFiled: March 3, 2021Date of Patent: January 24, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shinichi Kuwabara, Yasutaka Nakashiba
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Patent number: 11551999Abstract: A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.Type: GrantFiled: June 10, 2020Date of Patent: January 10, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lipu Kris Chuang, Chung-Shi Liu, Han-Ping Pu, Hsin-Yu Pan, Ming-Kai Liu, Ting-Chu Ko
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Patent number: 11545503Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.Type: GrantFiled: January 21, 2020Date of Patent: January 3, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Taekyung Kim, Kwang Soo Seol, Seong Soon Cho, Sunghoi Hur, Jintae Kang