Abstract: The present invention relates to a bias-switchable spectral response high performance PD with multi-mode detection, e.g., dual-mode photoresponses in NIR and visible light ranges. The dual-mode PD has the absorber/spacer type components in its active layer, e.g., a tri-layer configuration of absorber-1 (absorber-1 absorbs the electromagnetic wave of the first wavelength comprising visible light)/optical spacer/absorber-2 (absorber-2 absorbs the electromagnetic wave of the second wavelength comprising IR light). In the presence of IR light, photocurrent generates in the IR light absorbing layer under a reverse bias. In the presence of visible light, photocurrent generates in the visible light absorbing layer under a forward bias. A bias-switchable spectral response PD offers an attractive option for applications in environmental pollution, bio, medical, agricultural, automotive, fishery, food, wellness and security monitoring, detection and imaging in two or different or multiple distinct bands.

Abstract: Aspects of the invention include a method of tuning an interconnect that couples a first structure that is a first integrated circuit or a first laminate structure to a second structure that is a second integrated circuit or a second laminate structure. The method includes obtaining a compression requirement for a spring in a compliant layer of the interconnect. A longer path length of the spring leads to greater compression and mechanical support. Current and signal speed requirements for the interconnect are obtained. A shorter path length of the spring leads to greater current-carrying capacity and greater signal speed. Specifications for the spring are determined based on the compression requirement and the current and signal speed requirements. Determining the specifications includes determining a number of active coils of the spring to be less than two.

Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner.

Abstract: One embodiment includes: a substrate; a memory cell array that extends in a direction vertical to the substrate and includes a memory string having a plurality of series-coupled memory cells, and a selection transistor coupled to one end of the memory string; a wiring portion that includes a plurality of first conducting layers and a plurality of interlayer insulating films, the first conducting layers functioning as gate electrodes of the memory cell and the selection transistor, the interlayer insulating film being positioned between the first conducting layers in above and below directions; and a second conducting layer arranged on end portions of the plurality of first conducting layers of the selection transistor. The first conducting layers are electrically coupled in common to the second conducting layer.

Abstract: An inorganic light emitting diode device includes: a substrate including a plurality of sub-pixels; a thin film transistor (TFT) in each of the plurality of sub-pixels, wherein the TFT has at least one inorganic layer; an encapsulation layer on an organic light emitting layer, wherein the encapsulation layer includes at least one organic encapsulation layer and at least one inorganic encapsulation layer; and an opening exposing the inorganic layer of the TFT, wherein the opening connects the at least one inorganic encapsulation layer with the inorganic layer of the TFT.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.

Abstract: A method of manufacturing a semiconductor device may include: forming a fin-shaped structure on a substrate; forming a supporting layer on the substrate having the fin-shaped structure formed thereon, and patterning the supporting layer into a supporting portion extending from a surface of the substrate to a surface of the fin-shaped structure and thus physically connecting them; removing a portion of the fin-shaped structure close to the substrate to form a first semiconductor layer spaced apart from the substrate; growing a second semiconductor layer with the first semiconductor layer as a seed layer; and in at least a fraction of the longitudinal extent, removing the first semiconductor layer, and cutting off the second semiconductor layer on sides of the first semiconductor layer away from the substrate and close to the substrate, respectively, so that the cut-off second semiconductor layer acts as a fin of the device.

Abstract: Provided are a display panel and a display device. The display panel includes a base substrate, drive circuits, a light-blocking layer, organic light-emitting units, and fingerprint recognition units. Via holes and imaging apertures are formed in the light-blocking layer. The via holes include first via holes in communication with the imaging apertures and second via holes. Each of the first organic light-emitting units includes a first anode, and each of the second organic light-emitting units includes a second anode. The first anode and the second anode are electrically connected to the drive circuits through the first via holes or through the second via holes. In a first direction, a distance between an edge of the first anode facing close to the imaging aperture and a center of the first via hole is smaller than a distance between an edge of the second anode and a center of the second via hole.

Abstract: A semiconductor device including a lower structure, an upper pattern, a stacked structure, a separation structure passing through the stacked structure, a vertical structure comprising a channel layer, wherein the stacked structure comprises a plurality of interlayer insulating layers and a plurality of gate layers, the lower structure comprises a first lower pattern and a second lower pattern of a material different from a material of the first lower pattern, the first lower pattern comprises a first portion between the second lower pattern and the channel layer, a second portion extending from the first portion to a region between the second lower pattern and the upper pattern, and a third portion extending from the first portion to a region between the second lower pattern and the substrate structure, and the first lower pattern does not extend toward a side surface of the upper pattern.

Abstract: An organic light emitting display device may include a flexible substrate, a common layer, and an encapsulation member. An undercut groove may be formed on the flexible substrate. The common layer may be disposed on the flexible substrate, may include an organic light emitting layer, and may be disconnected by the groove. The encapsulation member may be disposed on the common layer, and may cover the common layer.

Abstract: Methods are disclosed herein that improve contours of trenches formed when fabricating vias and conductive lines of a multi-layer interconnect (MLI) structure. An exemplary device that can result from such methods includes a via of an MLI structure and a conductive line of the MLI structure disposed over the via. A first dielectric liner layer is disposed along sidewalls of the via and sidewalls of the conductive line. A thickness of the first dielectric liner layer is substantially the same along the sidewalls of the via. A thickness of the first dielectric liner layer increases along the sidewalls of the conductive line, such that the first dielectric liner layer has a tiger-tooth shape at each bottom corner of the conductive line. A second dielectric liner layer is disposed along the first dielectric liner layer that is disposed along the sidewalls of the via.

Abstract: A self light-emitting display device includes a substrate having a circuit board and a color filter pattern on the circuit board. The circuit board includes a driving thin-film transistor. The display device further includes a passivation film above the substrate, a color conversion pattern above the passivation film and overlapping the color filter pattern, and a light-emitting layer above the passivation film and the color conversion pattern. The light emitting layer includes a flat part and a convex part. The convex part is above the color conversion pattern and protrudes convexly relative to the flat part.

Abstract: A radiation-emitting semiconductor chip is disclosed. In an embodiment, a radiation-emitting semiconductor chip includes a semiconductor body configured to generate radiation, a first contact layer having a first contact area for external electrical contacting the semiconductor chip and a first contact finger structure connected to the first contact area, a second contact layer having a second contact area for external electrical contacting the semiconductor chip and a second contact finger structure connected to the second contact area, wherein the first contact finger structure and the second contact finger structure overlap in places, a current distribution layer electrically conductively connected to the first contact layer, a connection layer electrically conductively connected to the first contact layer via the current distribution layer and an insulation layer arranged in places between the connection layer and the current distribution layer, wherein the insulation layer has at least one opening.

Abstract: An organic light-emitting device is provided. The organic light-emitting device includes: an anode; a cathode; and an organic layer between the anode and the cathode and including an emission layer, wherein the emission layer includes a first emission layer including a first host, a second host, and a first dopant, and a second emission layer including a third host, a fourth host, and a second dopant, and the organic light-emitting device satisfies Equations 1 and 2.

Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.

Abstract: A semiconductor device includes a substrate, a first gate structure, a plurality of first gate spacers, a second gate structure, and a plurality of second gate spacers. The substrate has a first fin structure and a second fin structure. The first gate structure is over the first fin structure, in which the first gate structure includes a first high dielectric constant material and a first metal. A bottom surface of the first high dielectric constant material is higher than bottom surfaces of the first gate spacers. The second gate structure is narrower than the first gate structure and over the second fin structure, in which the second gate structure includes a second high dielectric constant material and a second metal. A bottom surface of the second high dielectric constant material is lower than bottom surfaces of the second gate spacers.

Abstract: A photosensor device and the method of making the same are provided. In one embodiment, the device includes at least one pixel cell. The at least one pixel cell includes a substrate formed from a semiconductor material, and includes first and second photosensor regions. The first photosensor region is disposed in the substrate and includes a first dopant of a first conductivity type. The second photosensor region is disposed above the first photosensor region and includes a second dopant of a second conductivity type. The second photosensor region can have an increase in dopant concentration from an outer edge to a center portion therein.

Abstract: A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.

Abstract: A highly reliable bonded structure having excellent thermal fatigue resistance characteristics and thermal stress relaxation characteristics is provided. The bonded structure of the present invention comprises a first member, a second member capable of being bonded to the first member, and a bonding part interposed between a first bond surface at the first member side and a second bond surface at the second member side to bond the first member and the second member. The bonding part has at least a bonding layer, a reinforcing layer, and an intermediate layer. The bonding layer is composed of an intermetallic compound and bonded to the first bond surface.

Abstract: An integrated multilayer structure, includes a substrate film having a first side and an opposite second side. The substrate film includes electrically substantially insulating material, a circuit design including a number of electrically conductive areas of electrically conductive material on the first and/or second sides of the substrate film, and a connector including a number of electrically conductive contact elements. The connector is provided to the substrate film so that it extends to both the first and second sides of the substrate film and the number of electrically conductive contact elements connect to one or more of the conductive areas of the circuit design while being further configured to electrically couple to an external connecting element responsive to mating the external connecting element with the connector on the first or second side of or adjacent to the substrate film.