Abstract: A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate. The gate stack includes a gate dielectric layer extending over a portion of the isolation feature, and a gate electrode over the gate dielectric layer. The low noise device further includes a charge trapping reducing structure adjacent to the isolation feature. The charge trapping reducing structure is configured to reduce a number of charge carriers adjacent an interface between the isolation feature and the channel.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes providing a substrate and depositing a conductive layer on the substrate. A patterned hard mask and a catalyst layer are formed on the conductive layer. The method further includes growing a plurality of carbon nanotubes (CNTs) from the catalyst layer and etching the conductive layer by using the CNTs and the patterned hard mask as an etching mask to form metal features.

Abstract: A transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device is provided. In a top-gate transistor in which an oxide semiconductor is used for a semiconductor layer where a channel is formed, elements are introduced to the semiconductor layer in a self-aligned manner after a gate electrode is formed. After that, a side surface of the gate electrode is covered with a structure body. The structure body preferably contains silicon oxide. A first insulating layer is formed to cover the semiconductor layer, the gate electrode, and the structure body. A second insulating layer is formed by a sputtering method over the first insulating layer. Oxygen is introduced to the first insulating layer when the second insulating layer is formed.

Abstract: A light emitting device includes at least one light emitting element to emit a first light having a first peak emission wavelength in a range of 420 nm to 480 nm and at least one fluorescent material to convert the first light to a second light having a second fluorescent peak wavelength in a range of 610 nm to 750 nm. The second light has chromaticity existing in an enclosed area in a CIE 1931 chromaticity diagram in which chromaticity is defined by x and y coordinates. The enclosed area is enclosed with a first straight line, a second straight line, a third straight line, and a curved line.

Abstract: A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped semiconductor substrate and divided into first, second, and third regions, with the third region forming the base. An insulating well is deeply implanted into the substrate. First and second third wells, respectively of N-type and P-type are formed to extend between the second region and third region and the insulating well. A third well of P-type is formed below the third region to provide the collector. Insulating layers are deposited over the third region and patterned to form an opening. Epitaxial growth of a second P-type doped semiconductor layer is performed in the opening to provide the emitter.

Abstract: The disclosure provides a manufacture method of a quantum dot light-emitting diode display and a quantum dot light-emitting diode display. The manufacture method of a quantum dot light-emitting diode display provided by the disclosure forms a light-emitting layer by a quantum dot thin film prepared by filming a metal complex solution, compared with a conventional ink jet printing method with quantum dot ink, process parameters can be adjusted easily, a process can be simple, costs can be reduced, three primary colors R, G, B can be adjusted by precisely controlling sub pixel levels, a color film can be omitted, which can be a better industrial design in weight and thickness. According to the quantum dot light-emitting diode display provided by the disclosure, the light-emitting layer is formed by a quantum dot thin film, which can offer the quantum dot light-emitting diode display excellent quality in display, the process is simple.

Abstract: The present invention generally relates to TFTs and methods for fabricating TFTs. For either back channel etch TFTs or for etch stop TFTs, multiple layers for the passivation layer or the etch stop layers permits a very dense capping layer to be formed over a less dense back channel protection layer. The capping layer can be sufficiently dense so that few pin holes are present and thus, hydrogen may not pass through to the semiconductor layer. As such, hydrogen containing precursors may be used for the capping layer deposition.

Abstract: Disclosed is a flexible display. The flexible display includes: a base layer which including a first portion having a first surface on which an organic light emitting element is disposed and a second portion extending from the outside of the first portion and bent toward a second surface opposing to the first surface; a protective film covering at least a part of the second portion to suppress permeation of moisture; a polarization layer disposed on the organic light emitting element of the first portion without having a barrier film between the polarization layer and the base layer; and a resin filled between the polarization layer and the protective film.

Abstract: A semiconductor device includes first and second Fin FET and a separation plug made of an insulating material and disposed between the first and second Fin FETs. The first Fin FET includes a first fin structure extending in a first direction, a first gate dielectric formed over the first fin structure and a first gate electrode formed over the first gate dielectric and extending a second direction perpendicular to the first direction. The second Fin FET includes a second fin structure, a second gate dielectric formed over the second fin structure and a second gate electrode formed over the first gate dielectric and extending the second direction. In a cross section a maximum width of the separation plug is located at a height Hb, which is less than ¾ of a height Ha of the separation plug.

Abstract: The invention provides a color filter array substrate and a manufacturing method thereof, and a display device. Multiple pixel units arranged in an array are formed on a base of the color filter array substrate, and each pixel unit includes a transparent region and an opaque region located at the periphery of the transparent region, the pixel unit further includes a color filter pattern and a black matrix pattern. The color filter pattern covers the transparent region, and the black matrix pattern directly covers the opaque region in the case of the color filter pattern being not disposed therebelow. Compared with the prior art, the invention can form a thicker black matrix pattern in the opaque region of the pixel unit to thereby prevent the light leakage problem, so that subsequent display quality can be improved.

Abstract: A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure. The chip package structure includes a first chip over the redistribution structure. The first chip has a front surface and a back surface opposite to the front surface, and the front surface faces the redistribution structure. The chip package structure includes an adhesive layer on the back surface. The adhesive layer is in direct contact with the back surface, and a first maximum length of the adhesive layer is less than a second maximum length of the first chip. The chip package structure includes a molding compound layer over the redistribution structure and surrounding the first chip and the adhesive layer. A first top surface of the adhesive layer is substantially coplanar with a second top surface of the molding compound layer.

Abstract: Provided is a deep ultraviolet LED with a design wavelength ?, including an Al reflecting electrode layer, an ultrathin metal layer, and a transparent p-AlGaN contact layer that are sequentially arranged from a side opposite to a substrate, and a photonic crystal periodic structure provided in the range of the thickness direction of the transparent p-AlGaN contact layer. The photonic crystal periodic structure has a photonic band gap.

Abstract: Electronic device comprising an interconnection structure comprising an alternating stack of arrays of conducting lines and dielectric layers in which: all the lines of a same array extend in a same plane and form an equipotential; a first pattern of a first array is such that the lines of the first array intersect at several intersections; a third pattern of a third array is similar, superimposed and aligned with the first pattern; a second pattern of a second array arranged between the first and third arrays is such that the lines of the second array intersect at several intersections offset with respect to those of the first and third patterns; a first conducting via extends from a line of the first and/or third array and is not in contact with the second array.

Abstract: An imaging sensor pixel comprises a highly resistive N? doped semiconductor layer with a front side and a back side. At the front side, there are at least a light sensing region, a transfer gate adjacent to the light sensing region and a P-well region. The P-well region surrounds the light sensing region and the transfer gate region, and comprises at least a floating diffusion region and a first electrode outside of the floating diffusion region, wherein a first negative voltage is applied to the first electrode. The transfer gate couples between the light sensing region and the floating diffusion region. At the back side, there is a back side P+ doped layer comprising a second electrode formed on the back side P+ doped layer, wherein a second negative voltage is applied to the second electrode. The second negative voltage is more negative than the first negative voltage.

Abstract: A semiconductor package may include a first output test pad and a second output test pad disposed on a first surface of an insulating film, and a semiconductor chip disposed between the first output test pad and the second output test pad on a second surface opposing to the first surface of the insulating film.

Abstract: A display device includes: a plurality of pixel electrodes respectively corresponding to a plurality of unit pixels that constitute an image; a light-emitting element layer stacked on the plurality of pixel electrodes so as to be in contact with each of the plurality of pixel electrodes and provided so as to emit light with a luminance controlled by an electric current; a common electrode provided so as to be stacked on and in contact with the light-emitting element layer above the plurality of pixel electrodes; and a sealing layer made of a light-transmissive material and stacked on the common electrode so as to seal the light-emitting element layer. The sealing layer is formed of a plurality of layers that are stacked on one another. The interface between two adjacent layers of the plurality of layers includes irregularities in regions located above the plurality of pixel electrodes.

Abstract: A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the active regions extending from a first surface of the wafer into the wafer by a height and being separated by separation regions, forming at least one trench in the wafer by plasma etching in at least one separation region from the first surface of the wafer. The at least one trench is extending into the wafer farther than the plurality of active regions. The method may further include processing a remaining portion of the wafer in the separation region to separate the wafer into individual chips.

Abstract: A semiconductor structure includes a first GAA transistor and a second GAA transistor. The first GAA transistor includes: a first top OD region, a first bottom OD region, and a first nanowire. A second GAA transistor includes: a second top OD region, a second bottom OD region, and a second nanowire. The first top OD region, the first bottom OD region, and the first nanowire are symmetrical with the second top OD region, the second bottom OD region, and the second nanowire respectively, the first GAA transistor is arranged to provide a first current to flow from the first top OD region to the first bottom OD region, and the second GAA transistor is arranged to provide a second current to flow from the second top OD region to the second bottom OD region.

Abstract: An interconnection structure includes a first dielectric layer, at least one first conductor, and an etch stop layer. The first conductor is disposed partially in the first dielectric layer and has a portion protruding from the first dielectric layer. The etch stop layer is disposed on the first dielectric layer and covers the protruding portion of the first conductor. The etch stop layer has a cap portion on a top surface of the protruding portion of the first conductor and a spacer portion on at least one sidewall of the protruding portion of the first conductor, and the spacer portion is thicker than the cap portion.