Abstract: Roughly described, a field effect transistor has a first piezoelectric layer supporting a channel, a second piezoelectric layer over the first piezoelectric layer, a dielectric layer having a plurality of dielectric segments separated by a plurality of gaps, the dielectric layer over the second piezoelectric layer, and a gate having a main body and a plurality of tines. The main body of the gate covers at least one dielectric segment of the plurality of dielectric segments and at least two gaps of the plurality of gaps. The plurality of tines have proximal ends connected to the main body of the gate, middle portions projecting through the plurality of gaps, and distal ends separated from the first piezoelectric layer by at least the second piezoelectric layer. The dielectric layer exerts stress, creating a piezoelectric charge in the first piezoelectric layer, changing the threshold voltage of the transistor.

Abstract: A memory structure includes a first dielectric layer, having a first top surface, over a conductive structure. A first opening in the first dielectric layer exposes an area of the conductive structure, and has an interior sidewall. A first electrode structure, having a first portion and a second portion, is over the exposed area of the conductive structure. The second portion extends upwardly along the interior sidewall. A resistance variable layer is disposed over the first electrode. A second electrode structure, having a third portion and a fourth portion, is over the resistance variable layer. The third portion has a second top surface below the first top surface of the first dielectric layer. The fourth portion extends upwardly along the resistance variable layer. A second opening is defined by the second electrode structure. At least a part of a second dielectric layer is disposed in the second opening.

Abstract: A device structure including a gate structure containing a first layer of carbon nanotubes and a second layer of carbon nanotubes. The first and the second layers are stacked vertically. The first and the second layers have carbon nanotubes which have substantially homogeneous electric characteristics within each layer. The carbon nanotubes in the first layer have different electric characteristics than the carbon nanotubes in the second layer, so that the device structure exhibits a multiple threshold behavior when coupled to a voltage source. The disclosure also includes a method for fabricating a multithreshold device structure.

Abstract: A semiconductor device includes a substrate, at least one integrated passive device, a first redistribution layer, a second redistribution layer, and conductive vias. The at least one integrated passive device includes at least one capacitor disposed adjacent to a first surface of the substrate. The first redistribution layer is disposed adjacent to the first surface of the substrate. The second redistribution layer is disposed adjacent to a second surface of the substrate. The conductive vias extend through the substrate, and electrically connect the first redistribution layer and the second redistribution layer.

Abstract: An opto-electronic apparatus and a manufacturing method thereof are disclosed. The manufacturing method of the opto-electronic apparatus includes the following steps of: disposing a matrix circuit on a substrate, wherein the matrix circuit has a matrix circuit thickness between the highest point of the matrix circuit and the surface of the substrate; disposing a plurality of first protrusions above the substrate, wherein at least one of the first protrusions has a first protrusion thickness between the highest point of the first protrusion and the surface of the substrate, and the first protrusion thickness is greater than the matrix circuit thickness; and performing a transfer step for transferring a plurality of first opto-electronic units from a first carrier to the first protrusions and bonding the first protrusions to at least two of the first opto-electronic units with an adhesive material.

Abstract: A semiconductor light-emitting device includes a substrate, an LED chip mounted on the substrate, and a resin package covering the LED chip. The substrate includes a base and a wiring pattern formed on the base. The resin package includes a lens. The base includes an upper surface, a lower surface and a side surface extending between the upper surface and the lower surface. The LED chip is mounted on the upper surface of the base. The side surface of the base is oriented in a lateral direction. The wiring pattern includes a pair of first mount portions and a pair of second mount portions. The paired first mount portions are formed on the lower surface of the base. The paired second mount portions are oriented in the lateral direction and offset from the side surface of the base in the lateral direction.

Abstract: A semiconductor device includes a first drain region that is made primarily of SiC, a drift layer, a channel region, a first source region, a source electrode that is formed on the first source region, a second drain region that is connected to the first source region, a second source region that is formed separated from the second drain region, a first floating electrode that is connected to the second source region and to the channel region, first gate electrodes, and a second gate electrode that is connected to the first gate electrodes.

Abstract: Techniques disclosed herein provide a method for pitch reduction (increasing pitch/feature density) for creating high-resolution features and also for cutting on pitch of sub-resolution features. Techniques include using multiple materials having different etch characteristics to selectively etch features and create cuts where specified. A sequence of materials or repeating pattern of lines of materials is used that provides selective self-alignment based on different etch resistivities. Combined with an underlying transfer or memorization layer, multiple different etch selectivities can be accessed. An etch mask defines which regions of the lines of multiple materials can be etched.

Abstract: An apparatus including an array of memory cells arranged in a grid defined by word lines and bit lines in a generally orthogonal orientation relative to one another, a memory cell including a resistive memory component and an access transistor, wherein the access transistor includes a diffusion region disposed at an acute angle relative to an associated word line. A method including etching a substrate to form a plurality of fins each including a body having a length dimension including a plurality of first junction regions and a plurality of second junction regions that are generally parallel to one another and offset by angled channel regions displacing in the length dimension an end of a first junction region from the beginning of a second junction region; removing the spacer material; and introducing a gate electrode on the channel region of each of the plurality of fins.

Abstract: Embodiments generally relate to apparatus and methods for dismantling a hermetically sealed chamber. In one embodiment, an apparatus facilitating the opening of a hermetically sealed chamber in a device comprises a fixture configured to hold the device, and a system configured to create sufficient tensile or shear stress at a bond interface of the seal to open the seal under controlled conditions. In one embodiment, a method for opening a hermetic seal between first and second elements forming a chamber in a microfluidic chip comprises using a release technique creating sufficient tensile or shear stress at a bond interface of the seal to open the seal under controlled conditions. The release technique comprises introducing a tool to the vicinity of the interface without any contact between the tool and any material within the chamber. The breaking of the seal results in the complete separation of the first and second elements.

Abstract: Methods and systems for reducing electrical disturb effects between thyristor memory cells in a memory array are provided. Electrical disturb effects between cells are reduced by using a material having a reduced minority carrier lifetime as a cathode line that is embedded within the array. Disturb effects are also reduced by forming a potential well within a cathode line, or a one-sided potential barrier in a cathode line.

Abstract: Multi-stack package-on-package structures are disclosed. In a method, a first stacked semiconductor device is formed on a first carrier wafer. The first stacked semiconductor device is singulated. The first stacked semiconductor device is adhered to a second carrier wafer. A second semiconductor device is attached on the first stacked semiconductor device. The second semiconductor device and the first stacked semiconductor device are encapsulated. Electrical connections are formed on and electrically coupled to the first stacked semiconductor device and the second semiconductor device.

Abstract: An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width. The length of each of the first lines is greater than the width. The integrated circuit also comprises a second layer on a second level different from the first level. The second layer comprises a set of second lines. The second lines each have a length and a width. The length of each of the second lines is greater than the width. The integrated circuit further comprises a coupling configured to connect at least one first line of the set of first lines with at least one second line of the set of second lines. The coupling has a length and a width. The set of second lines has a pitch measured between the lines of the set of second lines in the first direction. The length of the first coupling is greater than or equal to the pitch.

Abstract: A semiconductor device includes an active pattern, a gate electrode, a gate capping pattern, and a gate spacer. The active pattern extends in a first direction parallel to a top surface of the substrate. The gate electrode extends in a second direction parallel to the top surface of the substrate and intersects the active pattern. The gate capping pattern covers a top surface of the gate electrode and extends in a direction crossing the top surface of the substrate to cover a first sidewall of the gate electrode. The gate spacer covers a second sidewall of the gate electrode. The first sidewall and the second sidewall are opposite to each other in the second direction.

Abstract: This method concerns the protection against humidity of a device including a first and a second electronic components respectively having two opposite surfaces, the surfaces: being separated by a non-zero distance shorter than 10 micrometers; having an area greater than 100 mm2; being connected by an assembly of electrical interconnection elements spaced apart from one another by a space void of matter. This method includes applying a deposit of thin atomic layers onto the device to form a layer of mineral material covering at least the interconnection elements, the layer of mineral material having a permeability to water vapor smaller than or equal to 10?3 g/m2/day.

Abstract: A semiconductor package includes a redistribution layer (RDL) interposer having a first side, a second side opposite to the first side, and a vertical sidewall extending between the first side and the second side; at least one semiconductor die mounted on the first side of the RDL interposer; a molding compound disposed on the first side and covering the at least one semiconductor die and the vertical sidewall of the RDL interposer; and a plurality of solder bumps or solder balls mounted on the second side of the RDL interposer.

Abstract: The invention relates to an optoelectronic semiconductor component (1) comprising:—an optoelectronic semiconductor chip (2), comprising—a growth substrate (21) having a growth surface (21a),—a layer sequence (22) with a semiconductor layer sequence (221, 222, 223) with an active zone (222) grown on the growth surface (21a),—contact points (29) for electrically contacting the semiconductor layer sequence (221, 222, 223) and—and insulation layer (26), which is formed in an electrically insulting manner—a connection carrier (4), which is mounted to the cover surface (2a) of the optoelectronic semiconductor chip facing away from the growth surface (21a), wherein—the semiconductor layer sequence (221, 222, 223) is connected to the connection carrier (4) in an electrically conducting manner and—a conversion layer (5) is applied to a bottom surface (21c) of the growth substrate (21) facing away from the growth surface (21a) and to all side surfaces (21b) of the growth substrate (21).

Abstract: An interconnection structure includes a first dielectric layer, a first conductor, an etch stop layer, a second dielectric layer, and a second conductor. The first dielectric layer has at least one hole therein. The first conductor is disposed at least partially in the hole of the first dielectric layer. The etch stop layer is disposed on the first dielectric layer. The etch stop layer has an opening to at least partially expose the first conductor. The second dielectric layer is disposed on the etch stop layer and has at least one hole therein. The hole of the second dielectric layer is in communication with the opening of the etch stop layer. The second conductor is disposed at least partially in the hole of the second dielectric layer and is electrically connected to the first conductor through the opening of the etch stop layer.

Abstract: A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region.

Abstract: An optical sensor device includes a resin sealing portion for sealing an optical sensor element fixed to an element-mounting portion. The resin sealing portion is constituted of a resin having mixed and dispersed therein a glass filler obtained by pulverizing a phosphate-based glass which has spectral luminous efficacy properties by composition adjustment and high heat resistance and weatherability. The optical sensor device is highly reliable and capable of accommodating size and thickness reductions in packages and has stable and hardly changeable spectral luminous efficacy properties.