Patents Examined by Tuan Thai
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Patent number: 9665310Abstract: A storage control apparatus includes: a processor configured to execute a program for controlling access to a logical volume allocatable to a higher-level apparatus; and a storage configured to store the program, wherein the processor performs operations to: sets a value of identification information indicating whether notification of allocation to the higher-level apparatus is available in accordance with an order of recognition of a plurality of logical volumes to be allocated to the higher-level apparatus by the higher-level apparatus; and notifies the higher-level apparatus of information concerning one or more logical volumes of the plurality of logical volumes corresponding to the identification information.Type: GrantFiled: June 19, 2015Date of Patent: May 30, 2017Inventor: Jun Ishizaki
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Patent number: 9665435Abstract: A storage control apparatus controls storage units in a storage apparatus and includes a memory unit that stores group information identifying a copy-source volume group belonging to a consistency group; and a control unit that creates based on the group information, snapshots of respective volumes of the volume group for a given time point; creates respective difference storage areas to store, as difference data, update data for the respective volumes after the given time point; and transfers to a copy-destination storage apparatus, data of the snapshots of the respective volumes. The control unit further creates snapshots of the respective volumes at an arbitrary time point after the given time point; creates respective difference storage areas to store, as difference data, update data for the respective volumes after the arbitrary time point; and transfers to the copy-destination storage apparatus, the difference data of the respective volumes for the arbitrary time point.Type: GrantFiled: August 19, 2014Date of Patent: May 30, 2017Assignee: FUJITSU LIMITEDInventors: Kenichi Fujita, Takashi Kuwayama, Noboru Oguri
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Patent number: 9665507Abstract: Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains information which specifies whether the memory device is to commence outputting of a timing reference signal prior to commencing outputting of the data. The memory controller receives the timing reference signal if the information specified that the memory device output the timing reference signal. The memory controller subsequently samples the data output from the memory device based on information provided by the timing reference signal output from the memory device.Type: GrantFiled: May 11, 2011Date of Patent: May 30, 2017Assignee: Rambus Inc.Inventors: Ian Shaeffer, Thomas J. Giovannini
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Patent number: 9658926Abstract: Systems and methods are provided for performing a backup operation in a computing system. The source data and associated hardware are assessed to determine an optimum read block size and an optimum number of backup streams. The source data is then backed up using the optimum number of backup streams at the optimum read block size.Type: GrantFiled: July 8, 2014Date of Patent: May 23, 2017Assignee: EMC IP HOLDING COMPANY LLCInventors: Gururaj Kulkarni, Yogesh Suresh, Manjunatha Hebbar
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Patent number: 9652156Abstract: Managing data returns to a host in response to read commands, an operation monitor of a solid-state drive (SSD) manages counters used to hold metrics that characterize the estimated time to complete a read operation on a corresponding flash die. A timer generates a periodic event which decrements the counters over time. The value stored in each counter is generated for flash operations submitted to the corresponding die and is, generally, based on the operational history and the physical location of the operation. Whenever a read command is scheduled for submission to a particular die, the time estimate for that particular read operation is retrieved and, based on this information, the optimum order in which to return data to the host is determined. This order is used to schedule and program data transfers to the host so that a minimum number of read commands get blocked by other read commands.Type: GrantFiled: May 13, 2016Date of Patent: May 16, 2017Assignee: Western Digital Technologies, Inc.Inventors: Joao Alcantara, Zoltan Szubbocsev
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Patent number: 9645927Abstract: A module of cache coherence management by directory, in which each datum stored in cache memory is associated with a state, at least one of which indicates data sharing among a plurality of processors, the module including a storage unit to store a directory containing a list of cache memory addresses, each address possibly associated with a state corresponding to the state of the datum available at this address, and a processing unit configured to update said list, said processing unit being configured so as not to list the address lines related to data associated with the first state.Type: GrantFiled: June 19, 2015Date of Patent: May 9, 2017Assignee: BULL SASInventor: Thibaut Palfer-Sollier
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Patent number: 9645818Abstract: The information processing apparatus includes an arithmetic processing device configured to output an access request, a storage device configured to store data, a storage control device configured to accept the access request to the storage device from the arithmetic processing device, transfer the accepted access request to the storage device, and acquire a response to the access request from the storage device, and a diagnosis control device configured to send an access request to the storage device to the storage control device in place of the access request to the storage device from the arithmetic processing device, and acquire a response from the storage device via the storage control device.Type: GrantFiled: September 29, 2015Date of Patent: May 9, 2017Assignee: FUJITSU LIMITEDInventors: Makoto Suga, Koji Hosoe, Akio Tokoyoda, Masatoshi Aihara, Yuta Toyoda
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Patent number: 9645752Abstract: Systems and methods for utilization of notification or ordering commands are disclosed that can enable more efficient processing of flush requests from software programs and increase data consistency in storage devices. A storage device can obtain a notification command from a host system identifying one or more data items in a cache of the storage device, determine whether the one or more data items have been committed to non-volatile memory of the storage device, and transmit a notification to the host system upon determining that the one or more data items have been committed. The host system may utilize these commands to process flush requests, such that upon receiving a flush request, a notification command may be issued requesting a notification from the storage device that the relevant data has been committed.Type: GrantFiled: July 2, 2014Date of Patent: May 9, 2017Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventor: Nathan Obr
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Patent number: 9639462Abstract: Device for selecting a level for at least one read voltage for reading data stored in a multi-level memory device. The multi-level memory device includes a plurality of memory blocks, in which each of the memory blocks includes a plurality of word lines, each of the word lines being allocated to a plurality of memory pages and being indexed by a word line index. The device includes a first mapping unit for mapping each of the word line indices to one bin label, in which the number of bin labels is smaller than the number of word lines, and a second mapping unit for mapping each of the bin labels to a voltage information being indicative for at least one read voltage, in which the level for the at least one read voltage for reading data is selectable for each word line based on the respective word line index.Type: GrantFiled: December 12, 2014Date of Patent: May 2, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles J. Camp, Evangelos S Eleftheriou, Thomas Mittelholzer, Thomas Parnell, Nikolaos Papandreou, Charalampos Pozidis, Andrew Walls
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Patent number: 9639276Abstract: A request is received over a link that requests a particular line in memory. A directory state record is identified in memory that identifies a directory state of the particular line. A type of the request is identified from the request. It is determined that the directory state of the particular line is to change from the particular state to a new state based on the directory state of the particular line and the type of the request. The directory state record is changed, in response to receipt of the request, to reflect the new state. A copy of the particular line is sent in response to the request.Type: GrantFiled: March 27, 2015Date of Patent: May 2, 2017Assignee: Intel CorporationInventor: Robert G. Blankenship
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Patent number: 9632933Abstract: A plurality of processing units are interconnected by a coherency network in accordance with a directed spanning tree. Each processing unit that is a leaf of the directed spanning tree includes processing circuitry to provide a coherency response in response to a snoop request. Each processing unit which is not a root or leaf of the directed spanning tree includes switch point circuitry having one or more ingress ports coupled to neighboring processing units in accordance with the directed spanning tree. The switch point circuitry includes a coherency tracking table configured to store a combined coherency response in response to a particular snoop request based on one or more coherency responses received at the one or more ingress ports from the neighboring processing units.Type: GrantFiled: February 3, 2015Date of Patent: April 25, 2017Assignee: NXP USA, Inc.Inventors: Sanjay R. Deshpande, John E. Larson, Fernando A. Morales, Thang Q. Nguyen
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Patent number: 9632711Abstract: Systems and methods for utilization of notification or ordering commands are disclosed that can enable more efficient processing of flush requests from software programs and increase data consistency in storage devices. For example, when an application requests that a data cache be flushed, a computing device may—instead of completely emptying the data cache—notify the application of a successful flush once relevant data of the application has been committed to non-volatile memory. Targeted notifications, which may identify the relevant data in the data cache, can limit the scope of a flush request, such that the speed and efficiency of the command is increased relative to a non-specific full-cache flush. Such increases in efficiency of flush requests may greatly increase the speed and efficiency of storage devices, and consequently the performance of programs utilizing such storage devices.Type: GrantFiled: July 2, 2014Date of Patent: April 25, 2017Assignee: Western Digital Technologies, Inc.Inventor: Nathan Obr
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Patent number: 9632700Abstract: A method, system, and computer program product for managing a storage facility are disclosed. A potential file overlay may be detected when performing a file transfer. When a file is common to multiple systems and resides on a shared system storage volume, potential file corruption due to a data transfer request is detected and then able to be prevented. Hardware identifiers such as Universal Unique Identifiers (UUIDs) are used in managing a write of a file to shared system storage. By comparing multiple hardware identifiers, a determination is made as to whether to process the write of the file. If the hardware identifiers mismatch, the write is processed. If the hardware identifiers match, a potential file overlay is detected. Because of the potential file overlay, the write is aborted and a failure notification is returned. A successful overwrite prevention notification may also be returned.Type: GrantFiled: July 2, 2014Date of Patent: April 25, 2017Assignee: International Business Machines CorporationInventors: Kimberly T. Bailey, Samuel E. Reynolds, Wayne E. Rhoten, Andrew K. Tracy
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Patent number: 9632776Abstract: A processor provided with an instruction decoder responsive to preload instructions which trigger preload operations, such as page table walks and cache line fetches. An instruction decoder identifies if the memory address associated with the preload instruction matches a null value and suppresses the preload operation if the memory address does match the null value. The null value may be set under program control, it may be predetermined as a fixed value (e.g. zero) or may be set under hardware control, such as corresponding to memory addresses of a page identified by a memory management unit as non-accessible.Type: GrantFiled: March 7, 2011Date of Patent: April 25, 2017Assignee: ARM LimitedInventor: Simon John Craske
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Patent number: 9626116Abstract: Techniques are described for determining I/O workload. A first device of a first data storage system and a second device of a second data storage system are configured as synchronous mirrored devices of a first logical device. The host issues I/O operations to the first logical device over first and second paths. First I/O workload information is determined for a first data portion of the first logical device. Second I/O workload information is determined for the first data portion. The first I/O workload information and the second I/O workload information each include a first number of read operations that is a sum of read operations directed to the first logical device over both the first path and the second path. Data storage optimizations are performed on the first data storage system using the first I/O workload information and/or the second data storage system using the second I/O workload information.Type: GrantFiled: June 22, 2015Date of Patent: April 18, 2017Assignee: EMC IP Holding Company LLCInventors: Owen Martin, Benjamin Yoder, Arieh Don
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Patent number: 9619396Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.Type: GrantFiled: March 27, 2015Date of Patent: April 11, 2017Assignee: Intel CorporationInventors: Robert G. Blankenship, Jeffrey D. Chamberlain, Yen-Cheng Liu, Vedaraman Geetha
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Patent number: 9619404Abstract: Methods, apparatus and computer program products implement embodiments of the present invention that include defining, in a storage system including receiving, by a processor, metadata describing a first cache configured as a master cache having non-destaged data, and defining, using the received metadata, a second cache configured as a backup cache for the master cache. Subsequent to defining the second cache, the non-destaged data is retrieved from the first cache, and the non-destaged data is stored to the second cache.Type: GrantFiled: April 16, 2013Date of Patent: April 11, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David D. Chambliss, Ehood Garmiza, Leah Shalev
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Patent number: 9612776Abstract: The present embodiments describe systems and methods for a dynamically updated user data cache for persistent productivity. In an embodiment, the system includes caching mechanism optimized to support user productivity in the case of a primary storage failure. For example, an embodiment of a method includes establishing a cache for caching user data in a persistent data storage device that is accessible by a first operating system and a second operating system. The method may also include identifying a set of user data to be stored in the cache. Additionally, the method may include storing the set of user data into the cache. The method may also include accessing the set of user data stored in the cache with the second operating system in response to the first operating system being in a degraded condition.Type: GrantFiled: December 31, 2013Date of Patent: April 4, 2017Assignee: Dell Products, L.P.Inventors: Carlton A Andrews, Gary Douglas Huber, Manish Bhaskar, Munif Mohammed Farhan, Satya Mylvara, Todd Swierk, William F. Sauber, Philip M. Seibert
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Patent number: 9606909Abstract: Systems and methods are disclosed which facilitate management of thin provisioned data storage. Specifically, portions of thinly provisioned data stores may be deallocated when they contain invalid data, such as data deleted by a user. A user may transmit notifications, which may include write requests corresponding to a defined bit pattern, to a provider of the data store (or to the data store itself) that data has been deleted. A management component may modify the data store, or metadata corresponding to the data store, to reflect the deletion. The management component may further monitor portions of the data store to determine whether individual portions contain entirely invalid data. If so, the portion may be deallocated from the thin provisioned data store, resulting in more efficient thin provisioning. Deallocation may be enabled even where deletion notifications from a user do not correspond directly to allocated storage portions.Type: GrantFiled: April 5, 2013Date of Patent: March 28, 2017Assignee: Amazon Technologies, Inc.Inventor: Pradeep Vincent
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Patent number: 9600192Abstract: Methods, apparatus and computer program products for a distributed system include dividing logical volume data into data subsets, and defining at least one distributedly storage configuration for the logical volume. Metadata for the logical volume is written to a first set of first metadata tables, and the first set of first metadata tables is divided into metadata subsets having a one-to-one correspondence with the data subsets. The metadata subsets are distributed among the multiple digital information devices, and the metadata is copied from the first set of first metadata tables to a second set of corresponding second metadata tables in a one-to-one correspondence with the first metadata tables, and the second metadata tables are distributed among the multiple digital information devices.Type: GrantFiled: June 3, 2015Date of Patent: March 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: David D. Chambliss, Ehood Garmiza, Leah Shalev, Eliyahu Weissbrem