Abstract: Systems and methods for improved flash memory performance in a portable computing device are presented. In a method, a value N corresponding to an amount of prefetch data to be retrieved from the flash memory is determined. An access request for a flash memory is received at a cache controller in communication with a cache memory. A determination is made whether the access request for the flash memory corresponds to a portion of data stored in the cache memory. If the access request for the flash memory corresponds to the portion of data, the portion of data is returned in response to the access request. Otherwise, an N amount of prefetch data is retrieved from the flash memory and stored in the cache memory. The value N is incremented based on a cache hit percentage for the cache memory.

Abstract: A system and method for managing the storage of data in non-volatile memory is described. In an aspect, the data may be described by metadata and a transaction log file that are checkpointed from a volatile memory into the non-volatile memory. Actions that take place between the last checkpointing of a metadata segment and log file segment are discovered by scanning the non-volatile memory blocks, taking account of a record of the highest sector in each block that is known to have been recorded. Any later transactions are discovered and used to update the recovered metadata so that the metadata correctly represents the stored data.

Abstract: A computer-implemented method for writing data to a sequential storage medium, includes: writing plural data blocks sequentially to the sequential storage medium; and writing a data pattern to an area on the sequential storage medium, the area being an area to which none of the plural data blocks is written, the data pattern including plural bit patterns appearing in none of the plural data blocks, and thus representing that none of the plural data blocks is written to the area and representing specific information regarding the sequential storage medium.

Abstract: A method of operation of a device programming system includes: providing a target programmer, having a programming bus; coupling an electronic device, having a non-volatile memory, to the target programmer by the programming bus; and programming a data image into the non-volatile memory by the target programmer includes: subscribing to a broadcast message, receiving a logical block, of the data image, by the broadcast message for programming the non-volatile memory, and sending an unsubscribe message after receiving the logical blocks of the data image from the broadcast message.

Abstract: In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.

Abstract: A memory device includes a plurality of memory modules and a plurality of control lines. Each memory module includes a plurality of memory units. Each memory unit includes: a plurality of memory cell groups, each of which includes at least one memory cell; a plurality of first bit lines, each of which is coupled to the at least one memory cell of a respective memory cell group; a second bit line; and a plurality of controllable circuits, each of which has an input terminal coupled to a respective first bit line, an output terminal coupled to the second bit line, and a control terminal. Each control line is coupled to the control terminal of a corresponding controllable circuit of each of at least one memory unit of each memory module. The memory device consumes relatively small power.

Abstract: A data processing system and methods for performing cache eviction are disclosed. An exemplary method includes maintaining a metadata set for each cache unit of a cache device, wherein the cache device comprises a plurality of cache units, each cache unit having a plurality of segments, wherein each metadata set includes deletion hints (DH) metadata indicating whether the plurality of segments of a corresponding cache unit are valid. The exemplary method further includes in response to determining that a cache eviction is to be performed, selecting a predetermined number of cache units from the plurality of cache units, and determining a score for each of the selected cache units based on the DH metadata of the respective metadata set. The DH metadata may include, for example, a validation count for each segment group or cache unit. A deprecated segment can be changed back to being valid, and the score for each of the selected cache units may further be determined based on a determined probability.

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

Abstract: Systems and methods are provided for performing a backup operation in a computing environment. In an environment that includes virtual machines, a backup policy is established. The policy includes events that includes a control change rate. The events are used to drive the backup operation by causing virtual machines whose change rates satisfy the control change rate. Other virtual machines that do not satisfy the events may be omitted from the backup operation.

Abstract: Described are techniques for cache management that may include determining whether to flush dirty cached data included in a flash disk cache. Caching layer may include the flash disk cache as a secondary cache and another cache as a primary cache. Responsive to determining to flush dirty cache data from the flash disk cache, first processing may be performed that includes flushing dirty cached pages from the flash disk cache to one or more physical storage devices. The dirty cached pages may include data from a plurality of logical addresses of a first device. The logical address may be sorted and included in a sorted list. Flushing may include writing the plurality of dirty cached pages in an ordering in accordance with the sorted list.

Abstract: In a multithreaded data processing system including a plurality of processor cores, storage-modifying requests, including a translation invalidation request of an initiating hardware thread, are received in a shared queue. The translation invalidation request is removed and buffered in sidecar logic. While the translation invalidation request is buffered in the sidecar logic, the sidecar logic broadcasts the translation invalidation request so that it is received and processed by the plurality of processor cores. In response to confirmation of completion of processing of the translation invalidation request by the initiating processor core, the sidecar logic removes the translation invalidation request from the sidecar. Completion of processing of the translation invalidation request at all of the plurality of processor cores is ensured by a broadcast synchronization request.

Abstract: A storage apparatus acquires a data block including event data, time series information, first attribute information, and second attribute information. A first temporary accumulating unit and a second temporary accumulating unit temporarily accumulate the acquired data block in a first temporary storage unit and a second temporary storage unit, respectively. A first storing unit sorts a plurality of data blocks accumulated in the first temporary storage unit by the first attribute information and in a time series order identified from the time series information, and stores the sorted data blocks in a first storage unit. A second storing unit sorts a plurality of data blocks accumulated in the second temporary storage unit by the second attribute information and in a time series order identified from the time series information, and stores the sorted data blocks in a second storage unit.

Abstract: Methods for dynamically optimizing platform resource allocation of a logically-partitioned data processing system. Processor and memory resources are allocated to logical partitions of the data processing system. After allocating the processor and memory resources to the plurality of logical partitions, local and non-local memory accesses are monitored for the logical partitions. Based at least in part on the local and non-local memory accesses, a determination is made whether to reallocate the processor and memory resources of the logical partitions. Responsive to determining to reallocate the processor and memory resources, the processor and memory resources are dynamically reallocated to the logical partitions of the data processing system.

Abstract: A framework for performing transformations of logical storage volumes in software is provided. This framework interposes on various operations that can be performed on a logical storage volume, such as input/output (IO) operations, via one or more filters, which may be implemented by an appliance that is inserted into the data path of the operations issued to the logical storage volume.

Abstract: A computer-implemented method includes, in a transactional memory environment, identifying a transaction and identifying one or more cache lines. The cache lines are allocated to the transaction. A cache line record is stored. The cache line record includes a reference to the one or more cache lines. An indication is received. The indication denotes a request to demote the one or more cache lines. The cache line record is retrieved, and the one or more cache lines are released. A corresponding computer program product and computer system are also disclosed.

Abstract: A system and technique are provided for providing a service address space. The system includes a service co-processor provided with a service address space. The service co-processor is attached to a main processor wherein the main processor is provided with a main address space. The service address space and the main address space include a full range of memory available to the respective service-co-processor and the main processor. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service co-processor has a storage update receiving component for updating the service address space by receiving storage delta packets from the main processor and applying these to the service address space.

Abstract: Method and apparatus for locating data on disk storage, wherein multiple instances of data can be stored at different locations to satisfy different use requirements such as read access, write access, and data security. The method allows a data storage system, such as a file system, to provide both read optimized and write optimized performance on disk storage of different types (e.g., sizes and speed).

Abstract: A method and technique are provided for providing a service address space. The method includes providing a service co-processor with a service address space attached to a main processor. The main processor is provided with a main address space, and the service address space and the main address space include a full range of memory available to the respective service-co-processor and the main processor. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service address space is updated by receiving storage delta packets from the main processor and applying the storage delta packets to the service address space.

Abstract: Described herein are systems and methods to process efficiently, according to a certain order, a plurality of data sets arranged in data blocks. In one embodiment, a first compute element receives from another compute element a first set of instructions that determine an order in which a plurality of data sets are to be processed as part of a processing task. Relevant data sets are then streamed into a cache memory associated with the first compute element, but the order of streaming is not by order of storage but rather by the order conveyed in the first set of instructions.

Abstract: Described are techniques for processing I/O operations. A read operation is received to read first data from a first location. It is determined whether the read operation is a read miss and whether non-location metadata for the first location is stored in cache. Responsive to determining that the read operation is a read miss and that the non-location metadata for the first location is not stored in cache, first processing is performed that includes issuing concurrently a first read request to read the first data from physical storage and a second read request to read the non-location metadata for the first location from physical storage.