Abstract: A ferroelectric based capacitor structure and method for making the same. The capacitor includes a bottom electrode having a layer of Pt in contact with a first layer of an ohmic material. The capacitor dielectric is constructed from a layer of lead zirconium titanate doped with an element having an oxidation state greater than +4. The top electrode of the capacitor is constructed from a second layer of ohmic material in contact with a layer of Pt. The preferred ohmic material is LSCO; although RuO.sub.2 may also be utilized. The capacitor is preferably constructed over the drain of an FET such that the bottom electrode of the capacitor is connected to the drain of the FET. The resulting capacitor structure has both low imprint and low fatigue.

Abstract: In a semiconductor device having a polycide structure located on a stepped portion, halation during formation of a resist pattern is prevented, and oxidation of an upper surface of a high-melting-point metal silicide layer is prevented during formation of an interlayer insulating film on the polycide structure. In this semiconductor device, an upper layer which is formed of one layer selected from the group consisting of an amorphous silicon layer, a polycrystalline silicon layer, a TiN layer and a TiW layer is formed on the high-melting-point metal silicide layer forming the polycide structure. This effectively suppresses reflection of light beams by the upper layer located at the stepped portion during exposure for forming the resist pattern on the upper layer. Thereby, formation of a notch at the resist pattern is prevented, and the resist pattern is accurately formed to have a designed pattern.

Abstract: A gate electrode is made up of a polycrystalline silicon film containing phosphorous as a dopant for determining its conductivity type, a titanium silicide film of the C54 structure, and a tungsten silicide film all of which films are laid one on another in said order.

Abstract: A memory is described which has memory cells that store data using hot electron injection. The data is erased through electron tunneling. The memory cells are described as floating gate transistors wherein the floating gate is fabricated using a conductive layer of microcrystalline silicon carbide particles. The microcrystalline silicon carbide particles are in contact such that a charge stored on the floating gate is shared between the particles. The floating gate has a reduced electron affinity to allow for data erase operations using lower voltages.

Abstract: Disclosed herein is a semiconductor memory device including a plurality of memory cells each includes an active region which is defined in a column direction by a pair of trench isolation regions formed in a semiconductor substrate and in a row direction by an isolation gate conductor lines formed on a first gate insulating film covering the substrate, a source and a drain region selectively formed in the active region to define a channel region of a cell transistor, a second gate insulating film formed on the channel region, a word line formed on the second gate insulating film, a first insulating film covering the active region and the word line, a bit line formed on the first insulating film to overlap with the isolation gate conductor, a bit line connection conductor formed in the first insulating film to connect the drain region to the bit line with being in contact with the sidewall surface of the bit line, a second insulating film covering the bit line and the first insulating film, and a storage capac

Abstract: An electronic device characterized by a GaAs substrate and a base disposed n the substrate, the base comprising InAs channel layer, AlSb layer above the channel layer, In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer containing at least In, Al, and As disposed above the AlSb channel layer, InAs cap layer disposed above and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer disposed below the InAs channel layer and in contact with the substrate, p.sup.+ GaSb layer disposed within the AlSb layer, Schottky gate with a pad disposed on and in contact with the In.sub.x Al.sub.1-x As.sub.y Sb.sub.1-y layer, at least one ohmic contact disposed on the InAs cap layer, and a trench extending through the base to the substrate isolating the gate bonding pad from the device and providing a gate air bridge which prevents contact between the gate and the InAs layer.

Abstract: In a semiconductor device having a ferroelectric capacitor and manufacturing method thereof, a spacer comprising a low dielectric material is formed on the side surfaces of a plurality of lower electrodes separated into each cell unit, and a ferroelectric film is formed on the lower electrodes whereon the low dielectric material spacer is formed, and an upper electrode is formed on the ferroelectric film, to thereby prevent an error which may be caused between the adjacent lower electrodes.

Abstract: A self-aligned gate sidewall spacer and method of forming the sidewall spacer in a corrugated FET structure, comprising the steps of depositing a first oxide layer on a substrate; forming a substrate trench, having a substrate trench bottom and substrate trench sidewalls in the substrate; forming a gate electrode trench intersecting the substrate trench and filling the gate electrode trench with gate polysilicon for forming a gate electrode, the gate electrode having first and second gate sidewalls; depositing a second oxide layer over the gate electrode trench and substrate trench; and etching the second oxide layer for forming a sidewall spacer on each of the first and second gate sidewalls.

Abstract: A semi-conductor device having a conductive lead with an exposed tip disposed within a first insulative material, which is in turn disposed between insulated first and second integrated circuit chips is disclosed. The first insulative material is etched to form a recess after which a second insulative material is deposited on the access plane of the chips and within the recess. The tip of the wire lead is then exposed by either a chemical mechanical polish or by a wet etch/develop process.

Abstract: An electronic packaging module for inverted bonding of semiconductor devices, integrated circuits, and/or application specific integrated circuits is produced with protuberances on the conductive pattern of the substrate. The protuberances are of a soft, ductile metal capable of being metallurgically bonded to the input/output pads of semiconductor devices. The input/output pads of the semiconductor devices are simultaneously bonded to the protuberances of the packaging module.

Abstract: It is intended to provide a semiconductor circuit including thin-film transistors (TFTs) having a small leak current and TFTs capable of operating at high speed, and a method for manufacturing such a circuit. A material containing a catalyst element is selectively formed so as to be in close contact with an amorphous silicon film, or a catalyst element is selectively introduced into an amorphous silicon film. The amorphous silicon film thus processed is crystallized by illumination with laser light or strong light equivalent to it. A crystalline silicon area with a small amount of catalyst element is used for TFTs in a pixel circuit and a crystalline silicon area with a large amount of catalyst element is used for TFTs in peripheral circuits of an active matrix circuit.

Abstract: The invention has the object of realizing a semiconductor device in which the various problems brought about by parasitic diodes in configuring a circuit are prevented, the semiconductor device being provided with first and second insulated-gate field-effect transistors, and being configured such that the source regions of the first and second insulation gate field-effect transistors are electrically connected, the back gate region, which in part constitutes a channel, and the source region of the first insulated-gate field-effect transistor are electrically connected, and the back gate region of the second insulated-gate field-effect transistor is electrically connected to the drain region of the first insulated-gate field-effect transistor.

Abstract: The presently preferred embodiment of the invention provides a memory structure that eliminates the thick gate associated with the offset of the FAMOS transistor and reduces the standard 225 angstrom offset to a 100 angstrom offset required for FN tunnelling. The 100 angstrom offset is realized uniformly underneath the entire area of the floating poly. The invention uses transistors each having a 100 angstrom offset to realize both erase and programming functions. The present invention realizes an erasing feature through an erase transistor and an ERL line. However, the programming of the cell will be realized through the programming transistor. As a result, a double poly flash cell will function like an EEPROM. This functioning eliminates the hot electron tunnelling required to program conventional double poly flash cells and results in a significant reduction in chip real estate. The reduction allows the present invention to be scaled to next generation architectures.

Abstract: A non-volatile semiconductor memory device including a memory cell having a memory transistor and a selection transistor, comprising: a composite gate structure of the memory transistor formed on a surface of a semiconductor substrate at its first region with a first insulating film interposed therebetween and including a laminate of a floating gate electrode, a second insulating film and a control gate electrode; a gate electrode of the selection transistor formed on the surface of the semiconductor substrate at its second region close to the first region with a third insulating film interposed therebetween; and an impurity diffusion layer formed in the semiconductor substrate at its region between the first and second regions and functioning as a drain of the memory transistor, common to a source of the selection transistor, the impurity diffusion layer having at least an extension region extending to a part of the semiconductor substrate disposed under the composite gate structure, the extension region hav

Abstract: A nonvolatile memory cell (10) includes a single n-channel insulated gate FET (11) having a single floating gate (12). The FET (11) operates asymmetrically in a sense that the capacitance of a parasitic gate-source capacitor (24) is smaller than the capacitance of a parasitic gate-drain capacitor (26). The asymmetric condition is achievable either by fabricating the FET (11) as an asymmetric structure (30, 60) or by adjusting the capacitance of the parasitic capacitors (24, 26) through terminal biasing when the FET (11) is a short channel device. The potential of the floating gate (12) is controlled by biasing the source (14), drain (16), and substrate (18) of the FET (11). The cell (10) is programmed by moving charge onto the floating gate (12) via hot carrier injection, erased by moving charge from the floating gate (12) via tunneling, and read by sensing the conductive state of the FET (11).

Abstract: A capacitor having a pair of conductive electrodes separated by a dielectric layer and wherein at least one of the electrodes comprise Ti.sub.x Al.sub.1-x N, and wherein the variable "x" lies in a range of about 0.4 to about 0.8. The invention also contemplates a method for forming an electrically conductive diffusion barrier on a silicon substrate and which comprises providing a chemical vapor deposition reactor having a chamber; positioning the silicon substrate in the chemical vapor deposition reactor chamber; providing a source of gaseous titanium aluminum and nitrogen to the chemical vapor deposition reactor chamber; and providing temperature and pressure conditions in the chemical vapor deposition reactor chamber effective to deposit an electrically conductive diffusion barrier layer on the silicon substrate comprising Ti.sub.x Al.sub.1-x N, and wherein the variable "x" is in a range of about 0.4 to about 0.8.

Abstract: Disclosed is a three-dimensional integrated memory cell having a high interior volume and a method for constructing the same. The cell makes use of a highly conductive substrate material for the bottom electrode, allowing construction of a thin substrate without intolerable resistance. The substrate of the preferred embodiment, for example, comprises titanium silicide. The preferred method comprises conformal deposition of a thin polysilicon layer within a high aspect ratio container, followed deposition of a suitable metal for silicidation with the polysilicon layer. The metal need not be conformal for this preferred method and may be deposited by sputter deposition. After silicidation, excess metal is selectively etched away to leave a conformal, thin yet highly conductive substrate material.

Abstract: The structure and method is provided which prevents moisture and contamination from diffusing through openings (e.g., fuse windows) in insulating layers to product devices. Three moisture barrier layers form a moisture impervious boundary system to prevent moisture from diffusing from a fuse window into other overlying layers and into product devices. First and second barrier layers are formed insulation layers below the fuse. A third barrier layer is formed over an uppermost insulation layer, the sidewalls of a fuse window and over the fuse. The first and third barrier layers form a seal in the fuse area. The method comprises forming an insulating layer 52 54 over portions of said substrate 50 including in said fuse window area 63. A first barrier layer 56, a first interlevel dielectric layer 58 are formed over the insulating layer. A second barrier layer 60 is formed over said first interlevel dielectric layer 58.

Abstract: A top drain trench based RESURF DMOS (reduced surface field double diffused MOS) transistor structure provides improved RDSon performance by minimizing transistor cell pitch. The transistor includes a gate, a source and drain. The trench may include a nonuniform dielectric lining. A drain drift region partially surrounds the trench. Current flows laterally enabling multiple trench based RESURF DMOS transistors to be formed on a single semiconductor die. The addition of an isolation region to electrically isolate the source from the substrate allows the power transistor to be incorporated into high side driver applications as well as other application mandating electrical isolation between the source and ground.

Abstract: A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.