Abstract: A nonvolatile memory device includes a memory cell array having cell strings that each includes memory cells stacked on a substrate in a direction perpendicular to the substrate. A row decoder is connected with the memory cells through word lines. The row decoder applies a setting voltage to at least one word line of the word lines and floats the at least one word line during a floating time. A page buffer circuit is connected with the cell strings through bit lines. The page buffer senses voltage changes of the bit lines after the at least one word line is floated during the floating time and outputs a page buffer signal as a sensing result. A counter counts a number of off-cells in response to the page buffer signal. A detecting circuit outputs a detection signal associated with a defect cell based on the number of off-cells.

Abstract: Methods, systems, and devices for adjustable programming pulses for a multi-level cell are described. A memory device may modify a characteristic of a programming pulse for an intermediate logic state based on a metric of reliability of associated memory cells. The modified characteristic may increase a read window and reverse a movement of a shifted threshold voltage distribution (e.g., by moving the threshold voltage distribution farther from one or more other voltage distributions). The metric of reliability may be determined by performing test writes may be a quantity of cycles of use for the memory cells, a bit error rate, and/or a quantity of reads of the first state. The information associated with the modified second pulse may be stored in fuses or memory cells, or may be implemented by a memory device controller or circuitry of the memory device.

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and are also arranged in strings and configured to retain a threshold voltage within a common range of threshold voltages. A control circuit coupled to the plurality of word lines and the strings is configured to determine an erase upper tail voltage of a distribution of the threshold voltage of the memory cells following an erase operation. The erase upper tail voltage corresponds to a cycling condition of the memory cells. The control circuit is also configured to calculate a program voltage to apply to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells during a program operation based on the erase upper tail voltage.

Abstract: Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.

Abstract: The present application provides a memory test circuit and a device wafer including the memory test circuit. The memory test circuit is coupled to a memory array having intersecting first and second signal lines, and includes a fuse element and a transistor. The fuse element has a first terminal coupled to a first group of the first signal lines and a test voltage, and has a second terminal coupled to second and third groups of the first signal lines. The transistor has a source/drain terminal coupled to the second terminal of the fuse element and another source/drain terminal coupled to a reference voltage. The first group of the first signal lines are selectively coupled to the test voltage when the transistor is turned on, and all of the first signal lines are coupled to the test voltage when the transistor is kept off.

Abstract: A semiconductor device includes a plurality of input/output (I/O) pads; a serial input pad; a serial output pad; a plurality of interface circuits respectively corresponding to the I/O pads; and a plurality of option setting circuits respectively corresponding to the interface circuits, suitable for setting options of the respective interface circuits, wherein the serial input pad, the interface circuits, the option setting circuits, and the serial output pad configure a serial chain.

Abstract: A method of operating a controller that controls an operation of a semiconductor memory device including a meta area, a normal area, and a state area, includes sensing a turn-on of a memory system including the controller, checking a last state flag among at least one or more state flags stored in the state area, and determining whether to perform a reclaim operation on meta data stored in the meta area based on the checked state flag.

Abstract: A memory device includes a driver that drives a data line connected with an external device, an internal ZQ manager that generates an internal ZQ start signal, a selector that selects one of the internal ZQ start signal and a ZQ start command from the external device, based on a ZQ mode, a ZQ calibration engine that generates a ZQ code by performing ZQ calibration in response to a selection result of the selector, and a ZQ code register that loads the ZQ code onto the driver in response to a ZQ calibration command from the external device.

Abstract: The present invention provides a method for access a flash memory module, wherein the method includes the steps of: sending a read command to the flash memory module to read a plurality of memory cells of at least one word line of the flash memory module by using a plurality of read voltages, wherein each memory cell is configured to store a plurality of bits, each memory cell has a plurality of states, the states are used to indicate different combinations of the plurality of bits; obtaining readout information from the flash memory module; analyzing the readout information to determine numbers of the states of the memory cells; determining if the memory cells are balance or unbalance according the numbers of the states of the memory cells to generate a determination result; and referring to the determination result to adjust voltage levels of the plurality of read voltages.

Abstract: A storage device including: a peripheral circuit configured to perform a plurality of internal operations corresponding to a plurality of internal operation commands input from the memory controller, a temperature information controller configured to generate a first temperature code corresponding to an internal temperature at a time at which an internal operation corresponding to a first internal operation command among the plurality of internal operation commands is performed and temperature code generation information representing information that the first temperature code has been generated during a set period and a operation controller configured to control the peripheral circuit to perform an internal operation corresponding to a second internal operation command input after the first internal operation command among the plurality of internal operation commands is input, based on the first temperature code and the temperature code generation information, in response to the second internal operation com

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method of operating the memory system. According to embodiments of the present disclosure, a memory system may perform an integrity check operation on target code when information indicating whether a supply voltage supplied to a memory system is maintained at or below a first level for a first unit time is received from a voltage drop detector configured to sense a level of the supply voltage. Accordingly, the memory system is capable of minimizing the time of operation in the state in which a bit-flip occurs and preventing a problem in which irrecoverable data is recorded in a memory device due to malfunction of firmware.

Abstract: After a predetermined period of time in a life cycle of a flash memory device, a plurality of reliability values corresponding to a plurality of reads of one or more of the plurality of memory cells are generated; each of the reads using a variation of a predetermined read level voltage. An offset voltage is then identified, offset from the read level voltage. The offset voltage corresponds to a zero crossing point in the range of the reliability values. Once the offset voltage is identified, the read level voltage is set to a calibrated voltage based on the offset voltage.

Abstract: Techniques are provided for writing a high-level state to a memory cell capable of storing three or more logic states. After a sense operation performed by a first sense component and a second sense component, a digit line may be isolated from the first sense component and the second sense component. The high-level state may be stored in the memory cell, then a second state may be stored in the memory cell, in which the second state may be a mid-level state or a low-level state. The second state may be stored based on a write-back component identifying that the second state was stored in the memory cell before the write back procedure.

Abstract: A memory device, and a method of operating the same, includes a plurality of pages, a peripheral circuit, and control logic. The peripheral circuit is configured to receive a command, an address, and data from an external controller to program a page selected from among the plurality of pages, and to generate internal input data depending on an input mode for the command, the address, and the data. The control logic is configured to determine whether internal input data is to be generated based on the data depending on the input mode and to control the peripheral circuit so that a program operation of programming the internal input data is performed.

Abstract: The present technology includes a memory system and a method of operating the memory system. The memory system includes a memory device including an interface circuit, the interface circuit storing first system data, and a semiconductor memory; and a controller configured to output a read enable signal and a first read command for the first system data to the memory device. The semiconductor memory transfers a data strobe signal to the interface circuit in response to the read enable signal, the interface circuit reads the first system data in response to the first read command and transmits the read first system data to the controller in synchronization with the data strobe signal.

Abstract: A memory system includes: a plurality of memory dies, and a controller selects a second read request, including at least a portion of a plurality of first read requests, so that the memory dies interleave and output data corresponding to the first read requests, and performs a correlation operation for the selected second read request, when the second read request is selected, the controller determines whether the correlation operation is performed or not before a time at which the second read request is selected, determines whether the correlation operation is successful or not, determines a pending credit in response to an operation state of the memory dies at the time at which the second read request is selected, and determines whether to perform the correlation operation or not for the second read request that is selected at the time at which the second read request is selected based on the pending credit.

Abstract: The present invention relates to a method of operating memory cells, comprising reading a previous user data from the memory cells; writing a new user data and merging the new user data with the previous user data into write registers; generating mask register information, and wherein the mask register information indicates bits of the previous user data stored in the memory cells to be switched or not to be switched in their logic values; counting numbers of a first logic value and a second logic value to be written using the mask register information, respectively; storing the numbers of the first logic value and the second logic value into a first counter and a second counter, respectively; and applying a programming pulse to the memory cells according to the mask register information.

Abstract: A memory system includes a non-volatile memory and a controller configured to divides an n-dimensional space into a plurality of regions by a plurality of hyperplanes, assign a representative point of a read level for reading data from a plurality of memory cells to each region, trace a branch node in the binary tree by determining whether a first read level is higher or lower than a voltage level at the branch node of the binary tree, determine a read level of a representative point assigned to a region correlated with a leaf node among the plurality of divided regions as a second read level corresponding to the first read level when reaching the leaf node of the binary tree by tracing the branch node in the binary tree, and cause the memory to read data of the cells by applying a voltage of the second read level.

Abstract: Embodiments of the disclosure provide systems and methods for transmitting clock signals asynchronously to dual-port memory cells. A system according to embodiments of the disclosure may include a source clock configured to generate a clock signal, a dual-port memory cell having a first input port, and a second input port coupled to the source clock. A clock tuner coupled between the source clock and the first input port of the dual-port memory cell delays the clock signal by one of a plurality of delay times and transmits the clock signal to the first input port.

Abstract: The present disclosure relates to a storage device comprising a memory element. The memory element may comprise a changeable physical quantity for storing information. The physical quantity may be in a drifted state. The memory element may be configured for setting the physical quantity to an initial state. Furthermore, the memory element may comprise a drift of the physical quantity from the initial state to the drifted state. The initial state of the physical quantity may be computable by means of an initialization function. The initialization function may be dependent on a target state of the physical quantity and the target state of the physical quantity may be approximately equal to the drifted state of the physical quantity.