Abstract: A data storage device including a flash memory and a controller. The controller enables the flash memory to transmit a predetermined parameter stored in the flash memory according to a first predetermined trigger edge of a clock signal and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a first reference parameter in an asynchronous mode. The controller enables the flash memory to switch to a synchronous mode and transmit the predetermined parameter and reads the predetermined parameter transmitted by the flash memory according to the first predetermined trigger edge of the clock signal to obtain a second reference parameter in a detection mode.

Abstract: In an embodiment, a processor includes at least one core including a first core. The first core includes memory execution logic to execute one or more memory instructions, memory dispatch logic to output a plurality of memory instructions to the memory execution logic, and reactive memory instruction tracking logic. The reactive memory instruction tracking logic is to detect an onset of a memory instruction high power event associated with execution of at least one of the memory instructions, and to indicate to the memory dispatch logic to throttle output of the memory instructions to the memory execution logic responsive to detection of the onset of the memory instruction high power event. The processor also includes cache memory coupled to the at least one core. Other embodiments are described and claimed.

Abstract: Systems, methods, and other embodiments associated with conserving power using variable width pulses to activate word lines are described. In one embodiment, a memory device embedded within a processor. The memory device includes a pulse shaper to generate a first timing delay and a second timing delay according to power state information. The power state information indicates a current operating state of the processor. The memory device includes a memory controller to generate, in response to receiving a request to access one or more memory cells of the memory device, a word line enable signal that activates the one or more memory cells according to the first timing delay, the second timing delay, and a clock signal by generating the word line enable signal with a pulse width that is variable to conserve power when the state information indicates the processor is in a power saving state.

Abstract: An apparatus for data processing includes first and second functional units driven by corresponding first and second clock-signal sources, and a clock-retardation unit. The clock-retardation unit is configured to cause the second clock-signal to sustain a temporal offset that causes an offset between the first and second clock-signals to step toward a target time-domain offset between the first and second clock-signals.

Abstract: Methods, systems, and circuits for preserving state information during power saving operations are disclosed. One example embodiment includes a circuit having a processing core, where the processing core includes logic processing circuits as well as circuits (e.g., flip-flops registers) that are used to store state information in the processing core. The logic processing circuits have power connections to a power rail that are subject to a switch, which can disconnect the power connections from the power rail. The circuits that are used to store state information have different power connections that are subject to a different switch. Therefore, the logic processing circuits and the state information circuits can be separately power-collapsed.

Abstract: An electronic apparatus having an input unit and a network card and a wake-up method thereof are provided. In the method, an input event triggered by the input unit is received. Next, whether the electronic apparatus is in a partial wake-up mode entered after being woken up by the network card is determined. Then, the electronic apparatus is woken up to a normal operation mode if the electronic apparatus is in the partial wake-up mode.

Abstract: A non-transitory computer readable storage medium having stored thereon instructions executable by one or more processors to perform operations including: receiving a plurality of input parameters including (i) a workload type, (ii) a list of selected nodes belonging to a distributed computer system, and (iii) a list of frequencies; responsive to receiving the plurality of workload parameters, retrieving calibration data from a calibration database; generating a power estimate based on the plurality of workload parameters and the calibration data; and providing the power estimate to a resource manager is shown. Alternatively, the input parameters may include (i) a workload type, (ii) a list of selected nodes belonging to a distributed computer system, and (iii) an amount of available power, wherein the estimator may provide an estimation of the frequency at which the nodes should operate to utilize as much of the available power without exceeding the available power.

Abstract: An apparatus for controlling memory includes a memory controller, and an interface to data lines connecting it to memory. Each line carries a signal that corresponds to a bit to be written to memory. The interface includes, for each line, circuitry for transmitting a bit to memory via the line, and a data de-skewer. For each line, the de-skewer receives a first data signal that represents a bit to be written. Each line has an inherent skew. The de-skewer generates a second data signal by applying a skew to the first. A selected extent of skew increases a likelihood of sampling the second data signal during a data-valid window thereof. The same de-skewer receives and skews a first data bit read from the memory.

Abstract: Multiple ARM devices, each having multiple processing elements, linked together by an interconnect to form a coherent memory fabric in which each device has access to all of the processing elements located on all of the devices that are part of the coherent memory fabric. In order to comply with the ARM architecture, the system must have a global timer that is accessible to all of the ARM devices so that each of the devices can maintain the same timer value. The devices, systems, and methods disclosed herein provide for initial synchronization between multiple ARM devices that are joined together to form a coherent memory fabric. The initial synchronization is achieved by determining an offset between the timers of each ARM device and then minimizing the offset. The synchronization may be periodically checked and adjusted, as necessary, to maintain proper synchronization.

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for monitoring a task of a graphics processing unit (GPU) by a graphics driver, determining if the task is complete, determining an average task completion time for the task if the task is not complete and enabling a sleep state for a processing circuit for a sleep state time if the average task completion time is greater than the sleep state time.

Abstract: A portable device including a touch sensor configured to sense touch inputs, the touch sensor being in an active state while the portable device is in a standby mode; a touch sensor controller configured to receive the sensed touch inputs; and a processor configured to receive a signal from the touch sensor controller indicating whether the received sensed touch input indicates a first pre-stored pattern corresponding to a first active mode or a second pre-stored pattern corresponding to a second active mode, control the portable device to be in the first active mode based on the touch sensor controller receiving the signal indicating the sensed touch inputs correspond to the first pre-stored pattern, and control the portable device to be in the second active mode based on the touch sensor controller receiving the signal indicating the sensed touch inputs correspond to the second pre-stored pattern.

Abstract: A method for changing a support hardware configuration of a universal extensible firmware interface basic input output system (UEFI BIOS) is provided, and the change method is performed by a platform system. The method includes the following steps: in a boot stage, copying binary data of a setup menu in the UEFI BIOS to a memory or a storage medium, where a program of the setup menu to be displayed on a user interface is written in a visual forms representation (VFR) format, and a compiler compiles the program of the setup menu into the binary data of the setup menu in an internal forms representation (IFR) format; and writing a piece of address data to the UEFI BIOS, where the address data is used to query a location at which the binary data of the setup menu stored in the memory or the storage medium is located.

Abstract: A power supply apparatus includes a charging mode information receiving unit configured to receive, from each of a plurality of power receiving apparatuses each including a secondary battery, charging mode information indicating whether each of the power receiving apparatuses requests normal charging of the secondary battery or fast charging of the secondary battery, wherein the fast charging charges faster than the normal charging, a power supply order determination unit configured to determine a power supply order of the power receiving apparatuses based on the charging mode information, and a power supply unit configured to wirelessly supply power to the power receiving apparatuses in the order determined by the power supply order determination unit.

Abstract: A power conversion system includes a power transfer estimator that is operable to provide a determination of the cumulative amount of power transferred through the power supply, without additional sensing elements and at extremely low power levels, and to provide such determinations periodically over potentially long periods of time commensurate with the lifetime of a limited power source such as a battery. In a power conversion system operating in a discontinuous conduction mode (DCM), the power transfer estimator determines the charge transferred during each switching cycle, and the total number of switching cycles, to calculate the cumulative amount of power transferred. The power transfer estimator is optionally operable to calculate a value for the inductance to be used in the determination of the cumulative amount of power transferred through the power supply.

Abstract: Systems, methods, and firmware for power control of data storage devices are provided herein. In one example, a data storage device is presented. The data storage device includes a storage control system to identify a power threshold for the data storage device. The data storage device determines power consumption characteristics for the data storage device and enters into a power controlled mode for the data storage device that adjusts at least a storage transaction queue depth in the data storage device to establish the power consumption characteristics as below the power threshold for the data storage device.

Abstract: In an embodiment, a processor includes a master counter to store a time stamp count for the processor, and multiple cores each including a core counter to store core time stamp counts. The processor also includes synchronization logic to, in response to a de-synchronization event in a core: obtain a value of the master counter; initiate a first core counter using the value of the master counter, where the first core counter is included in the first core; compare a synchronization digit of the first core counter to a synchronization signal indicating a value of a synchronization digit of the master counter; and in response to a determination that the synchronization digit does not match the synchronization signal, adjust a first subset of digits of the first core counter based on a latency value of the synchronization signal. Other embodiments are described and claimed.

Abstract: A method for controlling an amount of power consumed by an integrated circuit. The method includes decoding a plurality of information units by performing a number of decoding iterations on each of the plurality of information units, and generating a moving average of decoding iterations performed when decoding a selected number of information units of the plurality of information units. The method further includes adjusting the number of decoding iterations based on (i) the moving average of decoding iterations performed in decoding the selected number of information units of the plurality of information units and (ii) the amount of power consumed by the integrated circuit.

Abstract: An electronic system includes: a storage unit configured to store a usage profile; a control unit, coupled to the storage unit, configured to retrieve the usage profile for a profile period, prepare an application during the profile period, and determine a power level from the usage profile for executing or offloading the application during the profile period.

Abstract: An embodiment of a power supply circuit to generate a supply voltage for a gate driver circuit can include an isolated power supply circuit to receive a first voltage in a first isolated system and provide power to a cyclic charging power supply circuit, the cyclic charging power supply circuit providing a supply voltage to the gate driver circuit in a second isolated system, the isolated power supply circuit providing the power to the cyclic charging power supply circuit while the gate driver circuit drives a transistor in an on state. The isolated power supply circuit can include a control circuit to regulate the power provided to maintain or increase the supply voltage while the gate driver circuit drives the transistor in an on state. The power supply circuit can also include the cyclic charging power supply circuit to receive a second voltage in the second isolated system and provide the supply voltage to the gate driver circuit.

Abstract: Booting a machine in a secure fashion in a potentially unsecure environment. The method includes a target machine beginning a boot process. The method further includes the target machine determining that it needs provisioning data to continue booting. The target machine contacts a secure infrastructure to obtain the provisioning data. The target machine provides an identity claim that can be verified by the secure infrastructure. As a result of the secure infrastructure verifying the identity claim, the target machine receives a request from the secure infrastructure to establish a key sealed to the target machine. The target machine provides the established key to the secure infrastructure. The target machine receives the provisioning data from the secure infrastructure. The provisioning data is encrypted to the established key. The target machine decrypts the encrypted provisioning data, and uses the provisioning data to finish booting.