Abstract: A technique for booting an information processing system includes storing a boot sequence table in a storage unit. The boot sequence table includes a specific boot sequence defining a boot sequence of a setup utility and a bootable subject during booting. The boot sequence table is accessed via the operating system firmware interface. A subject to be booted is determined in accordance with the boot sequence.

Abstract: According to one embodiment, a method and apparatus for controlling an alarm operation in a terminal, by which a plurality of alarms are terminated in the terminal. The method includes setting at least one of multiple alarm groups, each alarm group including multiple alarms, in which the setting of the at least one alarm groups includes automatically setting termination of the plurality of alarms associated with the alarm group to correspond to termination of the alarm group.

Abstract: An integrated circuit includes a circuit including a plurality of functional blocks, a sensor associated with one of the plurality of functional blocks for sensing a state of activity thereof, and a sleep switch receiving an output from the sensor and placing the associated functional block in a sleep state in response to the sensed state of activity.

Abstract: A powered device, a power supply system and an operation mode selection method are provided. The power supply system includes a power sourcing equipment and the powered device. The powered device is electrically connected to the power sourcing equipment through an internet cable. The powered device includes a sensing module and a controlling module. The sensing module receives an internet signal from the power sourcing equipment through the internet cable, and outputs a switching signal according to the internet signal. The controlling module is used for selecting an operation mode of the powered device according to the switching signal.

Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

Abstract: A data storage device includes a device sleep state pin and device sleep state logic to allow the data storage device to store security keys and necessary device sleep state logic together in a volatile logical data storage element. The volatile logical data storage element may be on-chip or off-chip. Device sleep state logic parameters for powering down PHYs while in a device sleep state determine the power characteristics of the device sleep state.

Abstract: A clock generation system for an integrated circuit (IC) chip (e.g., a microcontroller) is disclosed that allows digital blocks and other components in the IC chip to start and stop internal clocks dynamically on demand to reduce power consumption.

Abstract: Disclosed are systems, methods and computer program products for encryption of disk based on pre-boot compatibility testing. An example method includes upon determining, by a processor, no test booting of the computer, performing one or more pre-boot compatibility tests to boot an operating system of the computer; upon detecting a successful test booting, performing booting the operating system of the computer or performing the one or more pre-boot compatibility tests again; upon detecting an unsuccessful test booting, restoring a process of ordinary booting of the operating system and performing an ordinary booting of the operating system; determining one or more encryption policies applicable to a pre-boot execution stage of the computer; and comparing results of the one or more pre-boot compatibility tests with the encryption policies to determine whether to apply a full disk encryption to the boot disk.

Abstract: In an embodiment, a processor has a core to execute instructions which includes a first cache memory, a clock generation logic to receive and distribute a first clock signal to a plurality of units of the core, and a core activity monitor logic to monitor activity of the core and, responsive to a miss in the first cache memory, to send a first restriction command to cause the clock generation logic to reduce delivery of the first clock signal to at least one of the units to a first frequency less than a frequency of the first clock signal. Other embodiments are described and claimed.

Abstract: A system clock signal distributed to electronic configurable and reconfigurable computing devices within a distributed computing system. The distributed computing devices, which may be dual-die chip carriers (DDCC), include input addressable data/clock ports on which system clock signals are accepted and may be propagated on one or more data/clock output ports. The input and/or output ports of various distributed computing devices may be configured and reconfigured according to system preferences or requirements.

Abstract: The present disclosure relates to a method and an arrangement for monitoring at least one battery, to a battery having such an arrangement, and to a motor vehicle having a corresponding battery that is used for safely monitoring the battery condition with a reduced amount of hardware. The at least one battery is monitored by analyzing measured variables of the at least one battery using at least one data processing device. The signals exchanged between the at least one battery and the at least one data processing device via a communication connection are monitored at least once.

Abstract: A circuit arrangement for a data processing system is configured to process data in multiple modules. The circuit arrangement is configured to provide a clock as well as a time base and/or a base of at least one further physical quantity for each of the multiple modules. The circuit arrangement also comprises a central routing unit, which is connected to several of the multiple modules. Via the central routing unit, the modules can periodically exchange data based on the time base and/or on the base of the at least one further physical quantity. The several modules are configured to process data independently of and in parallel to other modules of the several modules.

Abstract: This invention relates to both a method and device for booting up a device and online scrubbing utilizing a system on chip appliqué sensor interface module in a Space Plug-and-Play Avionics environment that incorporates Radiation Hardened by Design components.

Abstract: A method of reducing downtime in a node environment is disclosed. The method includes identifying an originating system board of a plurality of system boards that requires service where the originating system board includes a node operating on a processor. The method further includes identifying a target system board of the plurality of system boards where the target system board includes a target processor. The method further includes transferring operation of the node to the target processor before the originating system board is serviced, and operating the node on the target processor.

Abstract: The disclosed embodiments provide a power management system that supplies power to components in an electronic device. The power management system includes a system microcontroller (SMC) and a charger. During operation, the power management system accepts power from at least one of a power adapter and a solar panel. Next, the power management system supplies the power to components in the electronic device without using a converter circuit between the solar panel and the power management system.

Abstract: An information handling system includes a processor, an air moving system, a power system, and power demand reduction circuit. The air moving system is operable to cool the processor. The power system is operable to power the processor and the air moving system. The power demand reduction circuit is operable to detect a total power system power demand that will exceed a power system output capacity of the power system in response to a processor power demand from the processor and, in response, reduce an air moving system power provided to the air moving system such that the processor power demand will no longer cause the total power system power demand to exceed the power system output capacity. The air moving system power may be increased when a decrease in the processor power demand results in the two contributing to a total power system power that will not exceed the power system output capacity.

Abstract: Example systems, apparatus, and methods receive audio information including a plurality of frames from a source device, wherein each frame of the plurality of frames includes one or more audio samples and a time stamp indicating when to play the one or more audio samples of the respective frame. In an example, the time stamp is updated for each of the plurality of frames using a time differential value determined between clock information received from the source device and clock information associated with the device. The updated time stamp is stored for each of the plurality of frames, and the audio information is output based on the plurality of frames and associated updated time stamps. A number of samples per frame to be output is adjusted based on a comparison between the updated time stamp for the frame and a predicted time value for play back of the frame.

Abstract: Each node and volume in a storage cluster makes a decision whether to reduce power consumption based on lack of requests from client applications and nodes over a time period. Node configuration parameters determine how long to wait until idling a node or volume, and how long to wait while idle before performing integrity checks. A bid value is calculated by each node and reflects how much it will cost for that node to write a file, read a file, or keep a copy. A node with the lowest bid wins, and nodes that are idle have a premium added to each bid to ensure that idle nodes are kept idle. In an archive mode, writes bids are reversed, nodes with less capacity submit lower bids, fuller nodes fill up faster and are then idled, while empty or near empty nodes may remain idle before winning a write bid.

Abstract: A circuit arrangement for a data processing system is configured to process data in a plurality of modules. The circuit arrangement is configured such that each module is provided with at least one clock pulse, a time base and a base of at least one additional physical variable. The circuit arrangement also comprises a central routing unit to which the plurality of modules are coupled and via which the plurality of modules can periodically exchange data amongst themselves, based on the time base and/or the base of other physical variables. Each module is configured independently and parallel to other modules of the plurality of modules in order to process data. The circuit arrangement is employed in a corresponding method.

Abstract: A semiconductor device including a detector to compare an amplitude of an applicable signal with a specified threshold amplitude, and to output a detector output indicating whether or not the amplitude of the applicable signal is above a specified threshold amplitude, and an intermittent operation control circuit that receives the detector output, and also receives a first signal showing which mode among the multiple modes the standby mode state is in, and sets the detector to the on (enable) mode state when the input signal is above the specified threshold amplitude, and in all other cases intermittently operates the detector according to characteristics of the input signal in the mode shown by the applicable first signal.