Abstract: A display apparatus includes a first substrate including a plurality of pixel areas provided in a display portion, a second substrate coupled to the first substrate, and a routing portion disposed on an outer surface of the first substrate and an outer surface of the second substrate. The first substrate includes a dam pattern disposed along an edge of the display portion, a light emitting device layer including a light emitting device disposed on the dam pattern and in the plurality of pixel areas, and a trench pattern portion disposed near the dam pattern. The light emitting device is isolated by the trench pattern portion.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a glass substrate, with a plurality of first pads on a first surface of the glass substrate, a plurality of second pads on a second surface of the glass substrate that is opposite from the first surface, a plurality of through glass vias (TGVs), wherein each TGV electrically couples a first pad to a second pad, wherein the plurality of first pads have a first pitch, and wherein the plurality of second pads have a second pitch that is greater than the first pitch, a bridge substrate over the glass substrate, a first die electrically coupled to first pads and the bridge substrate, and a second die electrically coupled to first pads and the bridge substrate, wherein the bridge substrate electrically couples the first die to the second die.

Abstract: An integrated circuit with a SAR SRAM cell with power routed in metal-1. An integrated circuit with a SAR SRAM cell that has power routed in Metal-1 and has metal-1 and metal-2 integrated circuit and SAR SRAM cell patterns which are DPT compatible. A process of forming an integrated circuit with a SAR SRAM cell with DPT compatible integrated circuit and SAR SRAM cell metal-1 and metal-2 patterns.

Abstract: An image sensing device and a method for forming the same are disclosed. The image sensing device includes a substrate including photoelectric conversion elements, and a grid structure disposed over the substrate. The grid structure includes an inner grid layer, and an outer grid layer formed outside the inner grid layer to provide air layer formed at a side surface and a top surface of the inner grid layer.

Abstract: An integrated circuit device includes a gate stack disposed over a substrate. A first L-shaped spacer is disposed along a first sidewall of the gate stack and a second L-shaped spacer is disposed along a second sidewall of the gate stack. The first L-shaped spacer and the second L-shaped spacer include silicon and carbon. A first source/drain epitaxy region and a second source/drain epitaxy region are disposed over the substrate. The gate stack is disposed between the first source/drain epitaxy region and the second source/drain epitaxy region. An interlevel dielectric (ILD) layer disposed over the substrate. The ILD layer is disposed between the first source/drain epitaxy region and a portion of the first L-shaped spacer disposed along the first sidewall of the gate stack and between the second source/drain epitaxy region and a portion of the second L-shaped spacer disposed along the second sidewall of the gate stack.

Abstract: A display device includes: a display panel; and a color conversion panel overlapping the display panel, where the display panel includes a transistor disposed on a first substrate; a light-emitting element electrically connected to the transistor; and a passivation layer disposed between the transistor and the light-emitting element and including a first recess portion. The light-emitting element is disposed on the first recess portion, the color conversion panel includes a first color conversion layer, a second color conversion layer and a transmission layer, which are disposed between a second substrate and the display panel, and at least one selected from the first color conversion layer, the second color conversion layer and the transmission layer overlaps the first recess portion.

Abstract: A display device includes a first island that includes a first display element disposed on a substrate, a second island that includes a second display element disposed on the substrate and spaced apart from the first island, a plurality of connection parts that connect the first island to the second island, through parts formed between the plurality of connection parts and that penetrate into the substrate, and an encapsulation layer that seals the first and second islands, and that includes a first inorganic encapsulation layer and a second inorganic encapsulation layer. The encapsulation layer of the first island includes an organic encapsulation layer, and the encapsulation layer of the second island does not include an organic encapsulation layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; semiconductor layers over the substrate, wherein the semiconductor layers are separate from each other and are stacked up along a direction generally perpendicular to a top surface of the substrate; a dielectric feature over and separate from the semiconductor layers; and a gate structure wrapping around each of the semiconductor layers, the gate structure having a gate dielectric layer and a gate electrode layer, wherein the gate dielectric layer interposes between the gate electrode layer and the dielectric feature and the dielectric feature is disposed over at least a part of the gate electrode layer.

Abstract: An IC structure includes a fin structure, a contact overlying the fin structure along a first direction, and an isolation layer between the contact and the fin structure. The isolation layer is adjacent to a portion of the contact along a second direction perpendicular to the first direction.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Abstract: A display panel includes a first substrate, pixel structures, a first common pad, a second substrate, a second common electrode, a display medium and a conductive particle. The pixel structures are disposed on an active area of the first substrate. The first common pad is disposed on a peripheral area of the first substrate, and is electrically connected to first common electrodes of the pixel structures. The second common electrode is disposed on the second substrate. The conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. The conductive particle includes a core and a conductive film disposed on a surface of the core, where the conductive film has a main portion and raised portions, and a film thickness of each of the raised portions is greater than a film thickness of the main portion.

Abstract: The present disclosure discloses a display apparatus, including a substrate including a pixel area including a disconnected area which encloses a hole area, an organic light emitting diode formed in the pixel area and the disconnected area, a plurality of inorganic insulating layers disposed below the organic light emitting diode, a disconnection structure which is disposed in the disconnected area and encloses the hole area, and an internal dam which is disposed in the disconnected area and encloses the disconnection structure, and in which the disconnection structure includes an eave portion which is simultaneously formed with the internal dam and a trench which is formed by etching the plurality of inorganic insulating layers disposed below the eave portion, and the disconnection structure is configured to have a predetermined overhang and a predetermined depth by the eave portion and the trench structure.

Abstract: Provided are a display panel and a display device. The display panel includes a base substrate as well as, at a side of the base substrate, a plurality of sub-pixels arranged in an array, a power bus, a plurality of first power lines extending along a column direction and a plurality of second power lines extending along a row direction, where each of the plurality of first power lines is electrically connected to the plurality of the sub-pixels arranged along the column direction, and the plurality of first power lines and the plurality of second power lines are electrically connected in overlapping regions of vertical projection on the base substrate. The display panel further includes a plurality of connection units.

Abstract: A display panel includes: a substrate including an opening penetrating from an upper surface to a lower surface of the substrate; a light emitting diode in a display area around the opening and including: a pixel electrode; an opposite electrode; and an intermediate layer between the pixel electrode and the opposite electrode; and a thin film encapsulation layer on the light emitting diode and including an organic encapsulation layer and at least one inorganic encapsulation layer, wherein the opposite electrode and at least one organic material layer of the intermediate layer extend toward the opening, wherein a portion of the opposite electrode facing the opening protrudes further toward the opening than the at least one organic material layer and includes a burr covered by the organic encapsulation layer.

Abstract: A stretchable display device includes a plurality of grip areas in which a clamp is disposed, and a buffer area adjacent to the plurality of grip areas are defined; a plurality of pixel substrates which is disposed in the display area to be spaced apart from each other; at least one base substrate which is disposed in each of the plurality of grip areas; a plurality of first connection lines which is disposed in the display area and connects the plurality of pixels formed on the plurality of pixel substrates; a plurality of second connection lines disposed in the grip area; and a plurality of third connection lines which is disposed in the buffer area, connects the plurality of first connection lines and the plurality of second connection lines, and has a ductile breaking rate higher than that of the plurality of first connection lines.

Abstract: Provided herein are a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes an etch stop pattern having a top surface and a sidewall disposed over a gate stack having interlayer insulating layers alternately stacked with conductive patterns. The semiconductor device also includes a plurality of channel structures passing through the etch stop pattern and the gate stack. The semiconductor device further includes an insulating layer extending to cover the top surface and the sidewall of the etch stop pattern, wherein a depression is included in a sidewall of the insulating layer. The semiconductor device additionally includes a contact plug passing through the insulating layer so that the contact plug is coupled to a channel structure of the plurality of channel structures.

Abstract: A display apparatus includes a first substrate, a pixel structure, a second substrate, and an anti-reflection structure. The pixel structure is disposed on the first substrate, and has an active element and a pixel electrode electrically connected to the active element. The second substrate is disposed opposite to the first substrate. The anti-reflection structure is disposed on the second substrate and is located between the first substrate and the second substrate. The anti-reflection structure includes a first insulating layer and a metal layer. The first insulating layer is disposed on the second substrate. The metal layer is disposed on the first insulating layer. The first insulating layer is located between the second substrate and the metal layer. The first insulating layer has an opening, the metal layer has an opening, and the opening of the first insulating layer and the opening of the metal layer overlap with the pixel electrode.

Abstract: A display device includes a base layer including a first surface and a second surface, pixels and first lines that are disposed on the first surface, second lines disposed on the second surface and corresponding to the first lines, a multi-layered etch stopper layer disposed on the first surface and disposed between the base layer and the first lines, and via holes penetrating the base layer and the multi-layered etch stopper layer, the via holes connecting the first lines to the second lines. The multi-layered etch stopper layer includes a first etch stopper layer disposed on the first surface and surrounding each of the via holes, the first etch stopper layer including an inorganic layer, and a second etch stopper layer entirely disposed on the first surface including the first etch stopper layer, the second etch stopper layer being open in a region corresponding to the via holes.

Abstract: A three terminal spin-orbit-torque (SOT) device is disclosed wherein a free layer (FL) with a switchable magnetization is formed on a Spin Hall Effect (SHE) layer comprising a Spin Hall Angle (SHA) material. The SHE layer has a first side contacting a first bottom electrode (BE) and an opposite side contacting a second BE where the first and second BE are separated by a dielectric spacer. A first current is applied between the two BE, and the SHE layer generates SOT on the FL thereby switching the FL magnetization to an opposite perpendicular-to-plane direction. The SHE layer is a positive or negative SHA material, and may be a topological insulator such as Bi2Sb3. A top electrode is formed on an uppermost hard mask in each SOT device. A single etch through the FL and SHE layer ensures a reliable first current pathway that is separate from a read current pathway.

Abstract: A semiconductor device includes a plurality of nano-channel field-effect transistor stacks positioned adjacent to each other such that source-drain regions are shared between adjacent nano-channel field-effect transistor stacks, each nano-channel field-effect transistor stack including at least two nano-channel field-effect transistors and corresponding source/drain regions vertically separated from each other.