Abstract: A display device including a substrate; a display element layer on the substrate, the display element layer including light emitting devices; a circuit element layer between the substrate and the display element layer, the circuit element layer including signal lines and light transmitting areas which are located between the signal lines in a plan view and allow light to be transmitted therethrough; a first light blocking layer between the substrate and the circuit element layer, the first light blocking layer including first openings; and a second light blocking layer on the first light blocking layer, the second light blocking layer including second openings. The second light blocking layer includes second sub-light blocking layers disposed to be spaced apart from each other, the second sub-light blocking layers each having the second openings. The first openings of the first light blocking layer overlaps with an area between the second sub-light blocking layers.

Abstract: A semiconductor package is provided. The semiconductor package comprises a first substrate, a second substrate disposed on the first substrate, a first semiconductor chip disposed on the second substrate, and a stiffener extending from an upper surface of the first substrate to an upper surface of the second substrate, the stiffener not being in contact with the first semiconductor chip, wherein a first height from the upper surface of the first substrate to an upper surface of the first semiconductor chip is greater than a second height from the upper surface of the first substrate to an uppermost surface of the stiffener.

Abstract: Methods for forming a string of memory cells, an apparatus having a string of memory cells, and a system are disclosed. A method for forming the string of memory cells comprises forming a metal silicide source material over a substrate. The metal silicide source material is doped. A vertical string of memory cells is formed over the metal silicide source material. A semiconductor material is formed vertically and adjacent to the vertical string of memory cells and coupled to the metal silicide source material.

Abstract: The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.

Abstract: A display device includes: a substrate; a display area in which a plurality of pixels are arranged over the substrate; and a transmission area arranged inside the display area, where the transmission area is provided to overlap a component below the substrate, and a transparent organic layer including siloxane is arranged in the transmission area.

Abstract: A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

Abstract: An organic light emitting diode display device includes a substrate, a pixel structure, a first circuit transistor, a first lower electrode, a first upper electrode, and a planarization layer. The substrate has a display area and a peripheral area including a first circuit area, a second circuit area, and a blocking area positioned between the first and second circuit areas. The pixel structure is in the display area on the substrate. The first circuit transistor is in the first circuit area on the substrate. The first lower electrode is in the blocking area on the substrate. The first upper electrode is on the first lower electrode, and the first upper electrode and the first lower electrode constitute a first capacitor. The planarization layer is on the substrate, and has a first opening that overlaps the first capacitor in the blocking area.

Abstract: A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

Abstract: A method of manufacturing an electronic package is disclosed. The described method includes (a) placing an electronic component on at least one layer structure; (b) encapsulating the electronic component by an encapsulant in a pressureless way; and (c) forming at least one further layer structure at the layer structure to thereby form a stack beneath the encapsulated electronic component. A further described electronic package includes (a) a stack comprising at least one layer structure and at least one further layer structure; (b) an electronic component being placed on the stack; and (c) an encapsulant encapsulating the electronic component, wherein the encapsulant has been formed in a pressureless way. Further described is an electronic device comprising such an electronic package.

Abstract: A sensor device may include a base layer, and an ASIC element disposed on the base layer. The ASIC element may include a plurality of electrical contact points. The sensor device may include a MEMS element. The MEMS element may include a plurality of through-silicon vias. The sensor device may include a plurality of conductive contact elements. Each conductive contact element may be disposed between, and electrically coupling, a respective through-silicon via and a respective electrical contact point. The sensor device may include a protective layer disposed between the ASIC element and the MEMS element. The protective layer may be composed of material(s) having a physical property defined to permit the protective layer to mitigate stress forces directed from the ASIC element to the MEMS element, to prevent corrosion, and/or to prevent leakage current between electrical connections due to pollution and/or humidity.

Abstract: An organic electroluminescence device includes: an anode; an emitting layer; and a cathode, the emitting layer containing a first material, a second material and a third material, the first material being a fluorescent material, the second material being a delayed fluorescent material, the third material having a singlet energy larger than a singlet energy of the second material.

Abstract: A circuit board includes a board, first connection pads disposed on the board and arranged in a first direction, second connection pads disposed on the board and arranged in the first direction, the second connection pads spaced apart from the first connection pads in a second direction perpendicular to the first direction, and a driving chip disposed on the board between the first connection pads and the second connection pads. Each of the first connection pads includes a first conductive layer disposed on the board, a second conductive layer which entirely overlaps with the first conductive layer in a plan view, is disposed on the first conductive layer and is formed of a different material from that of the first conductive layer, and a third conductive layer entirely overlapping with the second conductive layer and disposed on the second conductive layer.

Abstract: A light emitting device includes an LED having a (e.g., top) light output surface, a ceramic phosphor, and an adhesive layer positioned to attach the top of the LED to the ceramic phosphor. In one embodiment the adhesive layer is composed of multiple separate patches (regions) that define at least one channel therebetween, with the channel being open to an environment to permit oxygen permeation. The adhesive layer can be applied by a patternable dispensing system.

Abstract: A semiconductor device includes a source region and a drain region of a first conductivity type, a body region of a second conductivity type between the source region and the drain region, a gate configured to control current through a channel of the body region, a drift zone of the first conductivity type between the body region and the drain region, a superjunction structure formed by a plurality of regions of the second conductivity type laterally spaced apart from one another by intervening regions of the drift zone, and a diffusion barrier structure disposed along sidewalls of the regions of the second conductivity type of the superjunction structure. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si.

Abstract: A display device includes a first display region, a second display region, a curved portion provided between the first display region and the second display region, a plurality of first control lines provided in the first display region and extending in a first direction in which the first display region and the second display region are arranged side by side, and a plurality of second control lines provided in the second display region and extending in the first direction. The first control lines and the second control lines are electrically connected via curved portion wiring lines formed in the curved portion.

Abstract: A self-assembled nanostructure comprises first domains and second domains. The first domains comprise a first block of a block copolymer material and an activatable catalyst. The second domains comprise a second block and substantially without the activatable catalyst. The activatable catalyst is capable of generating catalyst upon application of activation energy, and the generated catalyst is capable of reacting with a metal oxide precursor to provide a metal oxide. A semiconductor structure comprises such self-assembled nanostructure on a substrate.

Abstract: A light emitting display apparatus according to an exemplary embodiment of the present disclosure includes an insulating layer on a substrate and including a base portion and a protrusion portion having an uneven portion at a part of the base portion, a first electrode covering an upper portion of the base portion and a side portion and a upper portion of the protrusion portion and disposed along the shape of the uneven portion, a bank layer covering a part of the insulating layer and a part of the first electrode, and an emission layer on the first electrode and the bank layer, and a second electrode on the emission layer.

Abstract: A display device includes a light transmitting substrate in which pixels are arranged, the pixels having a light transmitting region that transmits external light and a light emitting region in which a light emitting element is disposed; a first light blocking layer that is disposed in the light emitting region and blocks the external light; a thin film transistor that is disposed on the first light blocking layer and controls a light emission of the light emitting element; a first insulating layer that covers an active layer of the thin film transistor; a second light blocking layer that is disposed on the first insulating layer so as to cover the thin film transistor and blocks the external light; and a first light blocking wall that is connected to the first light blocking layer and the second light blocking layer and blocks the external light.

Abstract: A manufacturing method of an image sensor including the following steps is provided. A substrate is provided. A light sensing device is formed in the substrate. A storage node is formed in the substrate. The storage node and the light sensing device are separated from each other. A buried gate structure is formed in the substrate. The buried gate structure includes a buried gate and a first dielectric layer. The buried gate is disposed in the substrate and covers at least a portion of the storage node. The first dielectric layer is disposed between the buried gate and the substrate. A first light shielding layer is formed on the buried gate. The first light shielding layer is located above the storage node and electrically connected to the buried gate.

Abstract: A connection body which comprises a base structure at least predominantly made of a semiconductor oxide material or glass material, and an electrically conductive wiring structure on and/or in the base structure, wherein the electrically conductive wiring structure comprises at least one vertical wiring section with a first lateral dimension on and/or in the base structure and at least one lateral wiring section connected with the at least one vertical wiring section, wherein the at least one lateral wiring section has a second lateral dimension on and/or in the base structure, which is different to the first lateral dimension.