Abstract: The accuracy of electronic design automation is increased by determining whether fill wires in a putative integrated circuit design should be effectively grounded or floating. For each signal wire in the putative design adjacent to the fill wires, a signal sensitivity value, which represents sensitivity of a given one of the plurality of signal wires to noise and timing, is determined. For each one of the fill wires, a fill sensitivity value is determined by: identifying coupling of each one of the fill wires to the adjacent signal wires; and calculating the fill sensitivity value as a combination of the signal sensitivity values of each of the adjacent signal wires for which the coupling has been identified. At least a portion of the fill wires are selectively effectively grounded based on the fill sensitivity value, to obtain a modified design.

Abstract: This disclosure describes exemplary electrified vehicle charging systems and methods for charging energy storage devices (e.g., battery packs) of the vehicles. An exemplary charging system may be configured to monitor the electrified vehicle for determining whether either a recoverable vehicle fault or a non-recoverable vehicle fault occurs during a charging event and to automatically command a charging sequence restart without unplugging a charging component from a vehicle inlet assembly in response to detecting the recoverable vehicle fault. The control system may also be configured to provide remote notification about the need to unplug and replug the charging component when the non-recoverable fault is detected or when greater than a predefined number of charging sequence restarts have been attempted.

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a beam structure and an electrode on an insulator layer, remote from the beam structure. The method further includes forming at least one sacrificial layer over the beam structure, and remote from the electrode. The method further includes forming a lid structure over the at least one sacrificial layer and the electrode. The method further includes providing simultaneously a vent hole through the lid structure to expose the sacrificial layer and to form a partial via over the electrode. The method further includes venting the sacrificial layer to form a cavity. The method further includes sealing the vent hole with material. The method further includes forming a final via in the lid structure to the electrode, through the partial via.

Abstract: Various embodiments provide for modeling a power and ground (PG) mesh for a circuit design placement process. For some embodiments, a reference PG mesh can be used to generate a PG mesh model for a circuit design. A PG mesh model can be generated for a circuit design by calculating how much routing resource is occupied by the reference PG mesh of the circuit design, and the resulting PG mesh model can be applied to the circuit design by removing a similar amount of routing resource from the circuit design during a placement circuit design flow. Additionally (or alternatively), a PG mesh model can be generated to comprise a set of metal obstructions that correspond to each macro of the circuit design, and the PG mesh model can be applied to the circuit design by adding the metal obstructions to one or more metal layers of the circuit design.

Abstract: A method includes receiving a source file specifying circuit components and electrical connections therebetween. At least a portion of the circuit components and electrical connections are within one or more of a set of logical hierarchical groupings, and a given one of the groupings has one or more electrical connections to at least another one of the groupings. The method also includes selecting an initial subset of the groupings based on one or more characteristics of respective ones of the set of groupings and performing individual logical optimization of respective ones of the initial subset. The method further includes determining a revised subset based on the one or more characteristics of the respective ones of the set of groupings as modified by the logical optimization, and performing global physical optimization of the circuit components and electrical connections based at least in part on the revised subset.

Abstract: An approach is described for a method, system, and product for generating radial bump patterns. According to some embodiments, the approach includes determining parameters for radial pattern generation in a precomputing phase, creating a radial pattern in a second stage, and generating a layout from the radial pattern in the second stage before manufacture a device embodying the radial pattern. In some embodiments, the radial pattern comprises rings having a number of rows where bump instances are placed and rotated such that they are perpendicular to a radius from a common center line. Furthermore, in some embodiments, the number of rows in a ring is generated pursuant to a set value or dynamically generate based on one or more optimization metrics.

Abstract: Aspects of the disclosure are directed to reducing clock-ungating induced voltage droop by determining a maximum frequency value associated with an output clock waveform; modulating a clock frequency of the output clock waveform for a first time duration based on a first programmable mask pattern or a first Boolean function; and determining if either the first programmable mask pattern or the first Boolean function should be changed. In accordance with one aspect, a voltage droop mitigation circuit includes a control logic for receiving an input clock waveform and a clock enable signal waveform and for outputting a gated clock enable signal waveform; a latch coupled to the control logic, the latch for holding a state of the gated clock enable signal waveform and a AND gate coupled to the latch, the AND gate for outputting an output clock waveform.

Abstract: A battery pack system, a control method thereof and a management device are provided. A battery pack is connected in series with a discharge circuit unit and a charge circuit unit; a battery management unit is to monitor a temperature of the battery pack, to periodically send, when the temperature of the battery pack is lower than a threshold, a turn-on-instruction to the discharge circuit unit and the charge circuit unit alternately to control the discharge circuit unit and the charge circuit unit to be alternately turned on in heating cycles; the discharge circuit unit is to be turned on according to the turn-on-instruction to enable electricity of the battery pack to flow into the energy storage unit in discharging-phase; and the charge circuit unit is to be turned on according to the turn-on-instruction to enable electricity of the energy storage unit to flow into the battery pack in charging-phase.

Abstract: A power management system includes a battery charging system, a power supplying system, a first switching module, and a second switching module. The power management system is switched between the battery charging system and the power supplying system via the first switching module and the second switching module. With a charging electric energy generated by the waveform generating module, the battery charging system could restore the aging battery or the battery with degraded performance to a better state when the batteries are charging. By sensing a battery state of batteries, the power supplying system provides a supplementing power to the batteries, and the supplementing power and a power of the batteries could be supplied to a load together.

Abstract: A method of designing a layout includes generating first routing tracks assigned to a first color group, generating second routing tracks assigned to a second color group, wherein a first routing track of the first routing tracks is between adjacent second routing tracks of the second routing tracks, and specifying a color stitching region connecting a selected first routing track of the first routing tracks with a selected second routing track of the second routing tracks of the layout, wherein the color stitching region represents a conductive region that connects a first conductive element represented by the selected first routing track with a second conductive element represented by the selected second routing track through an exposed portion of the selected first routing track, and wherein the exposed portion is at a removed portion of a sidewall structure surrounding the selected first routing track.

Abstract: An integrated circuit includes a first type-one transistor, a second type-one transistor, a third type-one transistor, and a fourth type-one transistor. The first type-one transistor and the third type-one transistor are in the first portion of the type-one active zone. The integrated circuit includes a first type-two transistor in the first portion of the type-two active zone. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a gate configured to have the first supply voltage of a second power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor.

Abstract: A method of fabricating a semiconductor device includes designing a layout, forming a photomask based on the layout, correcting an optical transmittance of the photomask, and performing a photolithography process using the photomask having the corrected optical transmittance to form a pattern on a substrate. The correcting the optical transmittance of the photomask includes creating an intensity map by capturing light that passes through the photomask, simulating the layout to create a virtual intensity map, and correcting an optical transmittance of a mask substrate of the photomask based on the intensity map and the virtual intensity map.

Abstract: Methods of fabricating semiconductor devices are provided. A method of fabricating a semiconductor device includes selecting a target pattern from a target design layout. The target pattern includes: a target net; a target via that is electrically connected to the target net; and a crossing net that is electrically connected to the target via on a different level from the target net. The method includes analyzing a peripheral pattern that is adjacent the target net. Moreover, the method includes generating a redundant net, and a redundant via that electrically connects the redundant net and the crossing net. Related layout design systems are also provided.

Abstract: A method for performing multiple simulations for a circuit using a first plurality of samples is provided. The method includes obtaining a model of the circuit based on a result of the simulations, determining a failure rate and a confidence interval of the failure rate for the circuit with the performance model. The method includes determining an importance distribution based on the failure rate for the first plurality of samples, wherein the importance distribution is indicative of a probability that a sample value for the circuit will fail the simulation, selecting a second plurality of samples based on the importance distribution, performing a second set of simulations using the second plurality of samples to reduce the confidence interval of the failure rate. When the confidence interval is larger than a value, obtaining an updated performance model and performing new Monte Carlo simulations with new samples.

Abstract: A circuit design is partitioned into a plurality of partitions during a first synthesis by a computer processor. After modification of the circuit design, the computer processor determines changed partitions and unchanged partitions of the circuit design. The computer processor then determines dependent partitions of the changed partitions. The changed partitions and the dependent partitions are re-synthesized by the computer processor into respective re-synthesized partitions, and the computer processor then combines the respective re-synthesized partitions and the unchanged partitions into a complete synthesized circuit design in a memory.

Abstract: Disclosed are embodiments to provide a multi-battery energy storage device. One embodiment comprises a first battery and a second battery, with a first circuit branch coupling a positive side of the first battery to a positive side of the second battery, a second circuit branch coupling a positive side of the first battery to a negative side of the second battery, a third circuit branch coupling the negative side of the first battery to the negative side of the second battery, and multiple switchable devices configured to control flow of current through corresponding branches. Other embodiments comprise other configurations and operations.

Abstract: Multiple debug boundaries are defined in a hardware accelerator. The location of debug boundaries can be defined by a human user, or can be determined by automated tools based on characteristics of the circuitry in the hardware accelerator. Each debug boundary includes one or more hardware memory elements that are in a first state to indicate the debug boundary has not yet been reached, and that are changed to a second state by the hardware accelerator to indicate the debug boundary has been reached during execution of the hardware accelerator. Providing multiple debug boundaries in a hardware accelerator aids in debugging the accelerator design by identifying a particular section of the hardware accelerator where the failure occurred. This information regarding location of a failure may be provided to a user or to synthesis and simulation tools for the hardware accelerator design.

Abstract: In some embodiments, a wireless power charging circuit includes a wireless power receiver configured to receive wireless power from a receive coil and to produce a first voltage; an open loop capacitor divider coupled to receive the first voltage from the wireless power receiver and configured to provide a second voltage, the second voltage being reduced from the first voltage; and a linear battery charger coupled to receive the second voltage from the open loop capacitor and configured to provide a charging voltage to provide to a battery coupled to the system.

Abstract: Disclosed is a method of fabricating an integrated circuit (IC) using a multiple (N>2) patterning technique. The method provides a layout of the IC having a set of IC features. The method further includes deriving a graph from the layout, the graph having vertices connected by edges, the vertices representing the IC features, and the edges representing spacing between the IC features. The method further includes selecting vertices, wherein the selected vertices are not directly connected by an edge, and share at least one neighboring vertex that is connected by N edges. The method further includes using a computerized IC tool to merge the selected vertices, thereby reducing a number of edges connecting the neighboring vertex to be below N. The method further includes removing a portion of the vertices that are connected by less than N edges.