Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.

Abstract: A method for correction of an optical proximity effect, comprising: parsing and dividing the periphery of a design pattern to obtain segments to process; for a segment having a corner comprising a segment side (101) and an adjacent side (102) forming a corner relation with the segment side, setting a target point according to the following principle: when the length of the adjacent side (102) is greater than a preset length, the target point is set at the location of the outer end point (104) of the segment side; when the length of the adjacent side (102) is less than or equal to the preset length, the target point is set between the vertex (103) of the corner and the outer end point (104) of the segment side, and the less the length of the adjacent side (102), the further the target point from the location of the outer end point (104); and adjusting, according to a simulation difference of the target point, the design pattern until it conforms to a design target.

Abstract: Methods and apparatuses are provided for use in monitor power levels at a shopping facility, comprising: central control system separate and distinct from a plurality of self-propelled motorized transport units, wherein the central control system comprises: a transceiver configured to wirelessly receive communications from the plurality of motorized transport units; a control circuit coupled with the transceiver; and a memory coupled to the control circuit and storing computer instructions that cause the control circuit to: identify available stored power levels at each of the plurality of motorized transport units; identify an available recharge station, of a plurality of recharge stations distributed throughout the shopping facility, at least relative to a location of the first motorized transport unit intended to be subjected to recharging; and wirelessly communicate one or more instructions to cause the first motorized transport unit to cooperate with an available recharge station.

Abstract: The present disclosure provides a PCBA detection method and a system based on 3D AOI and AXI. The method includes: preconfiguring graphical data in a part physical database; obtaining CAD data related to a PCB based on design data input from PCB design software; converting the generated CAD data, and generating 3D basic graphical data to generate a 3D physical model; extracting BOM information from the design data, searching the part physical database for matched graphical data based on the BOM information, if the matched graphical data is found, generating a 3D physical model based on the graphical data; if the matched graphical data is not found, generating corresponding image data based on obtained created data, to generate a 3D physical model; and generating standard 3D detection prototype data, outputting the standard 3D detection prototype data to 3D AOI and AXI for detection.

Abstract: An adapter and method for using a grasp-socket component with a handheld electronic device, the adapter including a base layer having a top and a bottom side, wherein the bottom side of the base layer connects to the handheld electronic device; and a top layer that includes a planar surface and a plurality of side walls, wherein the top layer is coupled to the base layer to form a partially-enclosed hollow space between the top side of the base layer and the planar surface of the top layer, wherein the top layer includes an elongated opening in the planar surface that is sized and shaped such that the grasp-socket component can be coupled to the top layer and such that the grasp-socket component can be moved to a plurality of positions along the top surface of the base layer by sliding the grasp-socket component within the partially-enclosed hollow space.

Abstract: At the boundary where the number of effective chips changes, at least three grid points of a chip grid intersect with the periphery of a wafer effective region, and a triangle connecting these three grid points together includes therein the wafer center. To design a semiconductor chip, this feature is used to determine, by an analytic process, candidate solutions including different numbers of effective chips. These candidate solutions are used to derive an advantageous solution.

Abstract: Various embodiments provide for partial selection-based (e.g., cut-based) model extraction from a layout of a circuit design, which can be used to generate a schematic extracted view for the circuit design and to back annotate a schematic of the circuit design. For some embodiments, the selection comprises a cut of a layout of a circuit design, where the cut may be defined (e.g., inputted) by a user through a graphical user interface that is presenting the layout.

Abstract: Systems, methods, media, and other such embodiments described herein relate to improved operation of test devices which verify circuit operations. One embodiment involves accessing a circuit design comprising a plurality of instances of one or more blocks, where each block of the one or more blocks is associated with a corresponding block test pattern comprising one or more test subpatterns. Each corresponding block test pattern is processed to identify independent test subpatterns, and then each instance is processed to identify each independent test subpattern for the circuit design. Similar types of independent test subpatterns are merged into a circuit design test pattern, such that at least two of the independent test subpatterns associated with the circuit design occupy shared test cycles within the circuit design test pattern.

Abstract: A low voltage threshold adjusting method is provided and includes the following steps: detecting whether a present voltage is lower than a low voltage threshold; detecting whether a present current exceeds a preset current threshold in response to that the present voltage is lower than the low voltage threshold; detecting whether a present temperature exceeds a preset temperature in response to that the present current exceeds the preset current threshold; checking whether a current state of charge (SOC) is higher than a preset SOC in response to that the present temperature does not exceed the preset temperature; and decreasing the low voltage threshold in response to that the current SOC is higher than the preset SOC.

Abstract: An electronic design automation (EDA) tool for executing topological and functional checks on an electronic circuit design (ECD) includes a processor and a memory that stores the ECD, graphical rules, and filter rules for executing the checks. The processor generates a test graph based on the ECD, replaces stretchable nodes with nested networks in the test graph to generate extended graphs, and decouples real edges and functional edges of each extended graph to generate real graphs and functional graphs, respectively. Based on the graphical rules, the processor executes the topological checks on an input graph of the ECD to identify real sub-graphs from the input graph that are isomorphic to a real graph. The processor further generates functional sub-graphs by combining a functional graph with each real sub-graph, and based on the filter rules, further executes the functional checks on the functional sub-graphs to identify output graphs.

Abstract: A simulated-evolution-based macro refinement method includes evaluating a score of each placed macro cell to be refined; generating a random number; determining whether the score satisfies a predetermined condition; placing the macro cell into a queue if the score associated with the macro cell satisfies the predetermined condition; and sorting and placing macro cells of the queue according to scores of the macro cells in the queue.

Abstract: The present disclosure relates to a method for electronic design verification. Embodiments may include providing, using a processor, an electronic design and determining one or more design violations based upon, at least in part, a structural observability filter. Embodiments may also include generating a violation trace based upon, at least in part, the one or more design violations and displaying the violation trace at a graphical user interface configured to allow a user to debug the one or more design violations. Embodiments may further include allowing the user to select at least one path to be waived at the graphical user interface and generating a new violation trace without the at least one path to be waived.

Abstract: A deteriorated capacity calculator calculates a deteriorated capacity that is a capacity reduced from the capacity of a cell in an initial state. A gas amount calculator calculates an amount of gas contained in a container for the cell, from the deteriorated capacity. A pressure calculator calculates a pressure inside the container for the cell from the amount of the gas, a volume of a void space of the container for the cell and the temperature of the cell. A pressure monitor outputs a control signal for stopping charging or discharging of the battery when the pressure inside the container for at least any one cell is equal to or greater than a threshold pressure.

Abstract: A control method of a wireless power transmitter and a wireless power transmitter. The method includes transmitting a first power with a first cycle; transmitting a second power with a second cycle, wherein the second cycle is greater than the first cycle; when a wireless power receiver is placed within a charging area and is detected by the first power, upon detecting the wireless power receiver by the first power, transmitting a third power to drive the wireless power receiver to transmit a search signal to the wireless power transmitter; and when the wireless power receiver is placed within the charging area and is not detected by the first power, using the second power to detect the wireless power receiver and drive the wireless power receiver to transmit the search signal to the wireless power transmitter.

Abstract: A galvanic isolation in the power electronics system of an electricity charging station having the following features: a rectifier (11) for connection of the charging station (10) to a public low-voltage network and a galvanically isolating DC voltage converter (12) having a high clock frequency and connected to the rectifier (11) and a corresponding electricity charging station.

Abstract: The present disclosure provides a pattern density analysis method for analyzing a local pattern density of a layout, the method comprising: obtaining a pattern attribute of each layout pattern located on a layout region to be analyzed; setting, for each layout pattern, a relevant window for the layout pattern based on the corresponding pattern attribute; calculating the pattern density of each relevant window; and selecting the maximum value of the pattern densities of the relevant windows as the maximum local pattern density of the layout, and selecting the minimum value of the pattern densities of the relevant windows as the minimum local pattern density of the layout.

Abstract: Disclosed are methods, systems, and articles of manufacture for implementing an electronic design having embedded circuits. These techniques identify a specification of an electronic design, a parameter for optimization, at least one optimization target for the parameter, and initial grids for the electronic design. An optimization map may be determined, by at one or more optimization modules that are stored at least partially in memory of and function in conjunction with at least one microprocessor of a computing system, for the electronic design at least by performing one or more analyses that refine the initial grids for the optimization map with respect to the parameter and the at least one optimization target. The electronic design may be implemented based at least in part upon the optimization map.

Abstract: The present disclosure relates to a system and method for routing in an electronic circuit design. Embodiments may include providing, using a processor, a hierarchical electronic design having a plurality of partitions, at least one routing blockage, a source pin location, and one or more sink pin locations. Embodiments may also include generating a routing wire network configured to connect the source pin location and the one or more sink pin locations to create one or more segments, wherein generating the routing wire network includes creating two or more feed-through ports at one or more of the plurality of partitions. Embodiments may further include applying a maze-routing approach to each of the one or more segments of the routing wire network to form a routed net associated with the hierarchical electronic design.

Abstract: A decoder is implemented in a field programmable gate array (FPGA) by performing logic simplification of binary expressions associated with the decoder. To perform the logic simplification, the binary expressions are arranged in a binary matrix. Further, a set of submatrices is formed based on the binary expressions such that rows of each submatrix have common data bits in one or more columns of each submatrix. Based on the common data bits, a set of subexpressions for each submatrix is formed. The set of subexpressions of each submatrix is mapped into look-up table clusters of the FPGA, thereby implementing the decoder in the FPGA.

Abstract: A method of generating, by a computing device, a 3D circuit layout based on a 2D circuit layout, the method comprising: assigning cells of first and second groups of circuit cells of the 2D circuit layout to first and second levels of the 3D circuit layout, the assignment of each circuit cell of the first and second groups being performed by: selecting, among at least one first row of a first level of the 3D circuit layout and at least one second row of a second level of the 3D circuit layout, the row having the greatest available space; and assigning the circuit cell to the selected row; and transmitting the 3D circuit layout to a manufacturing plant for fabrication.