Abstract: The invention is suited for use by a hardware designer for the purpose of logic synthesis and/or logic simulation. It can be used in the design of integrated circuits (ASICs) and programmable logic devices (PLDs), such as field-programmable gate arrays (FPGAs). The invention also relates to the field of hardware description languages (HDLs). Embodiments of the invention provide a computer-implemented system and method for facilitating the design of a digital circuit which comprises a plurality of logical constructs. The system is configured such that each time each logical construct is executed during a software simulation pass it is associated with a unique tag, wherein each tag can correspond to a physical aspect of a hardware representation of the design. The simulation is performed by repeated execution passes through code which implements the design, preferably wherein the same tags are associated with corresponding executions of the logical constructs during different simulation passes.

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract: The invention provides a charging apparatus and an operating method thereof. The charging apparatus includes a power conversion circuit, a feedback circuit, an identifier control circuit, and a low voltage trickle control circuit. The feedback circuit generates a feedback signal for the power conversion circuit, and the power conversion circuit correspondingly adjusts a charging power according to the feedback signal. The power conversion circuit provides the charging power to charge a battery device. The identifier control circuit determines whether to control the feedback circuit to change the feedback signal according to identifier information of the battery device. The low voltage trickle control circuit determines whether to control the feedback circuit to change the feedback signal according to a voltage of the charging power. When the low voltage trickle control circuit controls the feedback circuit to change the feedback signal, the feedback circuit ignores control of the identifier control circuit.

Abstract: A method of performing automated surface-mount package design includes obtaining physical inputs that include names and locations of top and bottom pins, and obtaining electrical inputs that include electrical parameters such as impedance. The method also includes automatically performing analysis and processing of the physical inputs and the electrical inputs. A design file for manufacture of the surface-mount package is automatically generated based on the performing the analysis and the processing. The design file specifies a number and material of layers of the surface-mount package.

Abstract: A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of features in a given layer of a given patterned structure and converting the physical design layout patterns into two-dimensional (2D) arrays comprising entries for different locations in the given layer of the given patterned structure with values representing presence of the features at the different locations. The method also includes training, utilizing the 2D arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating one or more synthetic 2D arrays utilizing the trained generator neural network of the GAN, a given synthetic 2D array comprising entries for different locations in the given layer of a new physical design layout pattern with values representing presence of the features at the different locations of the new physical design layout pattern.

Abstract: A charging station for electric automobiles having a removable and/or folding hood and a circumferential sealing strip. The hood has a marginal sealing surface and the charging station is configured in such a way that the sealing strip and the sealing surface together form a continuous seal when the hood rests on the charging station.

Abstract: A communication module is configured to obtain, from a first computing device associated with an energy receiver, an energy request. The energy request includes a location of the energy receiver and an amount of energy requested. A selection module is configured to generate a list of energy sources available to satisfy the energy request. The communication module is further configured to: transmit the list of energy sources to the first computing device for display; receive, from the first computing device, a selection of one energy source from the list of energy sources; and transmit, to the first computing device and a second computing device associated with the selected one energy source, a location at which the energy request is to be fulfilled. An energy transfer module is configured to selectively enable an electrical energy transfer from the selected one energy source to the energy receiver.

Abstract: A circuit design verification method suitable for use with a 2.5D transceiver device potentially having hundreds of dice mounted on an interposer. An illustrative method includes: (a) retrieving a design of a circuit that includes multiple integrated circuit dice connected via an interposer, each die having at least one contact for receiving or transmitting a digital signal conveyed by an interchip connection of the interposer, said circuit including an IO cell for each such contact; (b) obtaining a timing model for components of said circuit, the timing model accounting for propagation delays of said IO cells and propagation delays of said interchip connections; (c) performing a static timing analysis of the design using the timing model to determine data required times and data arrival times at each of said components; (d) comparing the data required times with the data arrival times to detect timing violations; and (e) reporting said timing violations.

Abstract: An optical proximity correction (OPC) whereby corner rounding may be effectively controlled, and a mask manufacturing method performed using the OPC method are provided. According to the OPC method, an inner edge is generated through decomposition of a layout, and a displacement (DISin_frag) of an inner fragment and a displacement (DISsel) of a selected fragment are calculated based on the inner edge to additionally displace a fragment, so as to manufacture a mask layout with minimized corner rounding without violating mask rule check (MRC).

Abstract: A method of modifying an integrated circuit (IC) design layout is provided. The method includes receiving a first IC design layout having first gate layout patterns and first interconnect layout patterns. Second gate layout patterns for a second IC design layout are then obtained from the first gate layout patterns according to a set of design rules associated with a technology node different from that of the first IC design layout. After determining scaling factors for the first IC design layout based on the first gate layout patterns and the second gate layout patterns such that each scaling factor corresponds to one of at least one shrinkable region and at least one non-shrinkable region in the first IC design layout, the first interconnect layout patterns are adjusted using the scaling factors to determine second interconnect layout patterns for the second IC design layout.

Abstract: The present disclosure relates to a computer-implemented method for use in design for manufacturing associated with a die or package. Embodiments may include providing, using a processor, an electronic design and displaying, at a graphical user interface, at least a portion of a layout associated with the electronic design. Embodiments may also include determining an expected thermal or centrifuge force manufacturing variation associated with the electronic design. Embodiments may further include allowing a user to insert, at the graphical user interface prior to signoff, a copper pillar bump or solder bump on at least a portion of the layout based upon, at least in part, the determined expected thermal or centrifuge force manufacturing variation. Embodiments may further include displaying the copper pillar bump or the solder bump on the layout at the graphical user interface.

Abstract: A method for timing optimization is disclosed. The method includes obtaining information on timing of paths in a chip, wherein the information includes a mean of slacks and a sigma of slacks of each of the paths, determining a sigma margin (SM) value each of the paths, the SM value being obtained by dividing the mean by the sigma, and determining that a first path of the paths is more critical than a second path of the paths, an SM value of the first path being smaller than that of the second path.

Abstract: A method for tailoring a bespoke processor includes generating first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application. The method includes gate cutting and stitching based on the first gate-level activity information to remove unusable gates from the general purpose processor design and reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application.

Abstract: A method of making a wireless charging device for an electronic device includes printing a decoration layer on a surface of a glass or glass-ceramic substrate using a non-conductive ink. A coil is printed on the decoration layer, and an electromagnetic interference absorber layer is applied over the printed coil.

Abstract: The present invention relates to low-heat wireless power receiving device and method for charging a battery with low heat by receiving a wireless power signal from a wireless power transmitting device. When a power receiving coil receives a wireless power signal, a control unit matches impedance by controlling an impedance matching/controlling unit, determines a charging load state of a power receiving unit in accordance with a time-lapse of charging the power receiving unit and a current level detected by a current detecting unit, and selectively turns on a low-heat transforming unit and a high-heat transforming unit in accordance with the selected charging load state, thereby charging the power receiving unit with minimum heat generation.

Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.

Abstract: A method for charging an auxiliary voltage source that provides power for at least one additional component, the additional component being in addition to an electric drive that is powered by a main voltage, is described. The method includes electrically connecting a protection and/or control circuit to the main voltage source via a DC-to-DC converter configured for power supply, and to the auxiliary voltage source via a reverse blocking valve. The method further includes electrically connecting the main voltage source to the auxiliary voltage source via a charging device. The method still further includes charging the auxiliary voltage source via the main voltage source.

Abstract: One aspect is a method that includes identifying a substantially uniform distribution of signal vias for a multi-layer circuit board based on a design file defining a layout. A signal via pitch is determined as a center-to-center distance between a neighboring pair of signal vias. The signal via pitch is compared to a target minimum drilling distance. A ground via is identified proximate the neighboring pair of the signal vias. Based determining that the signal via pitch of the neighboring pair is less than the target minimum drilling distance, at least one of the signal vias is positioned closer to the ground via such that after the positioning, the signal via pitch of the neighboring pair meets or exceeds the target minimum drilling distance. The design file is modified to include the positioning of the signal vias and is transmitted over a network to support circuit board manufacturing operations.

Abstract: A method is disclosed that includes: if there is a conflict graph including a sub-graph representing that each spacing between any two of three adjacent patterns of quadruple-patterning (QP) patterns in at least one of two abutting cells is smaller than a threshold spacing, performing operations including: identifying if one of edges that connect the three adjacent patterns of QP patterns to one another is constructed along, and/or in parallel with, a boundary between the two abutting cells; modifying multiple-patterning patterns of a layout of an integrated circuit (IC) to exclude patterns representing the sub-graph; and initiating generation of the IC from the modified multiple-patterning patterns, wherein at least one operation of identifying, modifying, or initiating is performed by at least one processor.

Abstract: Embodiments are disclosed for solving a Boolean formula generated from an input design using an iterative loop using a computer-implemented Boolean satisfiability solver. An example method includes accessing data qualifier signals indicating one or more variables in a Boolean formula. The example method further includes marking the one or more variables in the Boolean formula as data qualifier variables based on the respective data qualifier signals. The example method further includes instructing a computer implemented Boolean satisfiability solver to solve the Boolean formula using an iterative loop, where operation of the iterative loop is prioritized based on the data qualifier variables. Corresponding apparatuses and non-transitory computer readable storage media are also provided.