Abstract: A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

Abstract: A semiconductor structure includes: a plurality of calibration reference features disposed on a substrate and spaced apart from each other in a first direction; and a plurality of columns of first active features and a plurality of columns of second active features respectively disposed on opposite sides of the calibration reference features, wherein each of the columns of first active features is spaced apart from each other in a second direction, each of the columns of second active features is spaced apart from each other in the second direction, and the calibration reference features, the first active features, and the second active features are disposed on the same layer and are a portion of the substrate.

Abstract: A method includes depositing a first mask over a target layer; forming a first mandrel and a second mandrel over the first mask; forming first spacers on the first mandrel and second spacers on the second mandrel; and selectively removing the second spacers while masking the first spacers. Masking the first spacers comprising covering the first spacers with a second mask and a capping layer over the second mask, and the capping layer comprises carbon. The method further includes patterning the first mask and transferring a pattern of the first mask to the target layer. Patterning the first mask comprises masking the first mask with the second mandrel, the first mandrel, and the first spacers.

Abstract: Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

Abstract: A method of forming a semiconductor device includes depositing a first layer over a substrate and patterning the first layer using an extreme ultraviolet (EUV) lithography process to form a patterned layer and expose portions of the substrate. The method includes, in a plasma processing chamber, generating a first plasma from a gas mixture including SiCl4 and one or more of argon, helium, nitrogen, and hydrogen. The method includes exposing the substrate to the first plasma to deposit a second layer including silicon over the patterned layer.

Abstract: Disclosed are semiconductor device fabricating method and semiconductor device fabricated by the same. The method includes forming on a lower mask layer first upper mask patterns and sacrificial spacers that cover sidewalls of the first upper mask patterns, forming first holes in the lower mask layer below the first upper mask patterns, forming second holes in the lower mask layer not covered by the first upper mask patterns and the sacrificial spacers, forming second upper mask patterns filling a space between the sacrificial spacers on the lower mask layer and also forming sacrificial patterns filling the first and second holes, removing the sacrificial spacers, using the first and second upper mask patterns to etch the lower mask layer, and removing the sacrificial patterns.

Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

Abstract: The disclosure provides a method for manufacturing shallow trench isolations, providing a substrate comprising a storage cell area and a peripheral area of a storage device; etching the upper part of the substrate of the storage cell area using a first etching process to form a first shallow trench, and filling the first shallow trench with silicon oxide using a first deposition process; and etching the upper part of the substrate of the peripheral area using a second etching process to form a second shallow trench, and filling the second shallow trench with silicon oxide using a second deposition process; wherein the depth and characteristic dimension of the first shallow trench are smaller than the depth and characteristic dimension of the second shallow trench. The disclosure can avoid the silicon dislocation defect of the peripheral area and ensure the device shape and characteristic dimension of the storage cell area.

Abstract: A method for forming a semiconductor structure is provided. In one form, a method includes: providing a base, where the base includes first regions and a second region located between the first regions; forming a pattern definition layer on the base; forming discrete mask layers on the pattern definition layer, the mask layers and the base defining openings, where openings of the first regions serve as first openings, and an opening of the second region serves as a second opening; forming a filling layer in the second opening; and etching, using the mask layers and the filling layer as masks, the pattern definition layer exposed from the first openings, to form target patterns.

Abstract: A nanowire can include a first semiconductor portion, a second portion including a quantum structure disposed on the first portion, and a second semiconductor portion disposed on the second portion opposite the first portion. The quantum structure can include one or more quantum core structures and a quantum core shell disposed about the one or more quantum core structures. The one or more quantum core structures can include one or more quantum disks, quantum arch-shaped forms, quantum wells, quantum dots within quantum wells or combinations thereof.

Abstract: According to one embodiment, a semiconductor device includes a stacked body, a columnar portion, a first charge storage portion, and a second charge storage portion. The stacked body includes a plurality of electrode layers stacked in a first direction. The plurality of electrode layers includes a first electrode layer, and a second electrode layer. The columnar portion extends in the first direction in the stacked body. The first charge storage portion provides between the first electrode layer and the columnar portion. The second charge storage portion provides between the second electrode layer and the columnar portion. A first thickness in a second direction intersecting the first direction of the first charge storage portion between the first electrode layer and the columnar portion is thicker than a second thickness in the second direction of the second charge storage portion between the second electrode layer and the columnar portion.

Abstract: A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.

Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.

Abstract: Embodiments provide method for forming a connecting pad. The method includes: providing a substrate; sequentially forming a conductive layer, a first pattern definition layer and a second pattern definition layer on a surface of the substrate; sequentially forming three groups of patterns intersecting with each other at 120° on the second pattern definition layer, an intersection portion of the three groups of patterns forming a hexagonal pattern definition structure on the second pattern definition layer; transferring the pattern definition structure downward, and etching away a portion of the first pattern definition layer, such that the remaining first pattern definition layer forms a columnar structure, wherein a bottom of the columnar structure is circular in shape under an action of an etching load effect; and etching the conductive layer by using the remaining first pattern definition layer as a mask, such that the remaining conductive layer forms a circular connecting pad.

Abstract: A static random-access memory device is provided. The static random-access memory device includes a substrate with at least one first region; first fins on a surface of the substrate, and second initial fins on the surface of the substrate. A width of the second initial fins is different from a width of the first fins. A portion of the first fins is used to form pass-gate transistors, and another portion of the first fins and the second initial fins are used to form pull-down transistors.

Abstract: A semiconductor package may include a substrate; a microelectromechanical device disposed on the substrate; an interconnection structure connecting the substrate to the microelectromechanical device; and a metallic sealing structure surrounding the interconnection structure.

Abstract: In described examples, a packaged semiconductor device includes a frame, a pre-fabricated interposer, and an integrated circuit die. The frame includes multiple conductive frame leads and multiple conductive connection points, as well as a hole in the frame surrounded by the frame leads and the conductive connection points. The pre-molded interposer has an external perimeter including multiple conductive interposer leads, and is for insertion into the hole. At least one of the interposer leads does not extend to the external perimeter of the interposer. The die is electrically coupled to selected ones of the frame leads and of the interposer leads. The interposer is inserted into the hole and coupled to the frame, and the frame, interposer, and die are together encapsulated by encapsulation material.

Abstract: An integrated circuit includes a first circuit with m first units coupled in parallel, any of the first units including one or more first transistors coupled in series, and a second circuit with n second units coupled in parallel, any of the second units including one or more second transistors coupled in series. A gate terminal of the first circuit is coupled to a gate terminal of the second circuit. M and n are different positive integers.

Abstract: The present application provides a method for improving the metal work function boundary effect in FinFET process, the method comprises steps of: depositing a first TiN layer on four fin structures. The first TiN layer has no gap between the second and the third fin structures; removing the first TiN layer up to a first distance from the midline between the second and third fin structures at the second fin structure side; depositing a second TiN layer; removing the second and first TiN layers from second fin structure. The thickness of the TiN layer at the bottom edge of the fin structure at the later structure of the ultra-low threshold voltage P-type transistor will be smaller from this process. Thus formed TiN layer is less prone to a bottom undercut during etching, thereby reducing the metal boundary effect and increasing of the threshold voltage of the device.

Abstract: An IC fabrication method includes forming a first fin on a semiconductor substrate, forming an isolation dielectric material over the first fin, and planarizing the isolation dielectric material. A top surface of the first fin is covered by the isolation dielectric material after planarizing the isolation dielectric material. The method further includes etching back the isolation dielectric material until the first fin protrudes from the isolation dielectric material.