Abstract: Processes to form differently-pitched gate structures are provided. An example method includes providing a workpiece having a substrate and semiconductor fins spaced apart from one another by an isolation feature, depositing a gate material layer over the workpiece, forming a patterned hard mask over the gate material layer, the patterned hard mask including differently-pitched elongated features, performing a first etch process using the patterned hard mask as an etch mask through the gate material layer to form a trench, performing a second etch process using the patterned hard mask as an etch mask to extend the trench to a top surface of the isolation feature, and performing a third etch process using the patterned hard mask to extend the trench into the isolation feature. The first etch process includes use of carbon tetrafluoride and is free of use of oxygen gas.

Abstract: Embodiments are described herein that apply capping layers to cores prior to spacer formation in self-aligned multiple patterning (SAMP) processes to achieve vertical spacer profiles. For one embodiment, a plasma process is used to deposit a capping layer on cores, and this capping layer causes resulting core profiles to have protective caps. These protective caps formed with the additional capping layer help to reduce or minimize material loss and corner loss of the core material during spacer deposition and spacer etch processes. This reduction in core material loss improves the resulting spacer profile so that a more vertical profile is achieved. For one embodiment, an angle of 80-90 degrees is achieved for vertical sidewalls of the spacers adjacent core sites with respect to the horizontal surface of the underlying layer, such as a hard mask layer formed on a substrate for a microelectronic workpiece.

Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.

Abstract: Various embodiments provide a thickness sensor and method for measuring a thickness of discrete conductive features, such as conductive lines and plugs. In one embodiment, the thickness sensor generates an Eddy current in a plurality of discrete conductive features, and measures the generated Eddy current generated in the discrete conductive features. The thickness sensor has a small sensor spot size, and amplifies peaks and valleys of the measured Eddy current. The thickness sensor determines a thickness of the discrete conductive features based on a difference between a minimum amplitude value and a maximum amplitude value of the measured Eddy current.

Abstract: A semiconductor chip includes a first cell row constituted by I/O cells arranged in the X direction and a second cell row constituted by I/O cells arranged in the first direction, spaced from the first cell row by a predetermined distance in the Y direction. A plurality of external connecting pads include pads each connected with any of the I/O cells and a reinforcing power supply pad that is not connected with any of the I/O cells and is connected with a pad for power supply. The reinforcing power supply pad is placed to lie in a region between the first cell row and the second cell row.

Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate, and forming a first core layer on the substrate. The substrate includes a pull-up transistor region. The method also includes forming separately arranged second core layers on the first core layer, and forming a first sacrificial sidewall spacer on a sidewall of a second core layer. A gap is formed between adjacent first sacrificial sidewall spacers over the pull-up transistor region. In addition, the method includes removing the second core layers, and then etching the first core layer using the first sacrificial sidewall spacers as a mask until the substrate is exposed. The gap is transferred to a region between adjacent etched first core layers over the pull-up transistor region. Further, after etching the first core layer, the method includes forming a dielectric layer to fully fill the gap.

Abstract: The present disclosure provides a method for preparing a semiconductor device structure with fine boron nitride spacer patterns. The method includes undercutting a photoresist pattern over a semiconductor substrate, and forming an inner spacer element over a sidewall surface of the photoresist pattern. The inner spacer element has a portion extending into a recess (i.e., the undercut region) of the photoresist pattern to form a footing, and a width of the portion of the inner spacer element increases continuously as the portion extends toward the semiconductor substrate. As a result, the inner spacer element may be prevented from collapsing after removal of the photoresist pattern.

Abstract: Provided is a method of manufacturing a semiconductor device. The method includes providing a substrate in which a main area including a first cell area and a first peripheral area, and an edge area including a second cell area and a second peripheral area are defined, sequentially forming a mold layer, a supporter layer, a mask layer, and a preliminary pattern layer on the substrate, exposing the preliminary pattern layer to light to simultaneously form a first pattern and a second pattern on the mask layer of the first cell area and the second cell area, respectively, forming an etch stop layer on the second pattern and etching the mask layer using the etch stop layer and the first pattern to form a hole pattern in the mold layer and the supporter layer of the first cell area.

Abstract: Methods to manufacture integrated circuits are described. Nanocrystalline diamond is used as a hard mask in place of amorphous carbon. Provided is a method of processing a substrate in which nanocrystalline diamond is used as a hard mask, wherein processing methods result in a smooth surface. The method involves two processing parts. Two separate nanocrystalline diamond recipes are combined—the first and second recipes are cycled to achieve a nanocrystalline diamond hard mask having high hardness, high modulus, and a smooth surface. In other embodiments, the first recipe is followed by an inert gas plasma smoothening process and then the first recipe is cycled to achieve a high hardness, a high modulus, and a smooth surface.

Abstract: A semiconductor substrate includes a dielectric insulation layer and a structured metallization layer having at least five separate sections attached to the dielectric insulation layer, a first switching element having first emitter and collector terminals, a second switching element having second emitter and collector terminals, a first diode element having first anode and cathode terminals, and a second diode element having second anode and cathode terminals. The switching and diode elements are arranged on a first section of the metallization layer, with the collector and cathode terminals electrically coupled to the first section. The first anode and emitter terminals are electrically coupled to second and third sections. The second anode and emitter terminals are electrically coupled to fourth and fifth sections. The first section separates the second and fourth adjacent sections from the third and fifth adjacent sections.

Abstract: Disclosed is a semiconductor device including a semiconductor die, a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess on its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

Abstract: The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate defined with a peripheral region and an array area at least partially surrounded by the peripheral region; disposing an insulating layer over the substrate; disposing a capping layer over the insulating layer; disposing a hardmask stack on the capping layer; patterning the hardmask stack; removing portions of the capping layer exposed through the hardmask stack; removing portions of the insulating layer exposed through the hardmask stack; removing portions of the substrate exposed through the capping layer and the insulating layer to form a plurality of fins in the array area and a first elongated member at least partially surrounding the plurality of fins; removing the hardmask stack; and forming an isolation over the substrate and surrounding the plurality of fins and the first elongated member.

Abstract: Semiconductor devices and fabrication methods thereof are provided. The method may include forming a first sacrificial film on a to-be-etched layer having; and forming second sacrificial layers on the first sacrificial film. A first trench or a second trench is between adjacent second sacrificial layers; and a width of the second trench is greater than a width of the first trench. The method also includes forming a first sidewall spacer on a sidewall surface of a second sacrificial layer, a ratio between the width of the first trench and a thickness of the first sidewall spacer being greater than 2:1; and etching the first sacrificial film using the first sidewall spacer as an etching mask to form first sacrificial layers. A third trench or a second trench is between adjacent first sacrificial layers. The method also includes forming a second sidewall spacer to fill the third trench.

Abstract: A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×102 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.

Abstract: A semiconductor structure and a method for forming the same are provided. The method includes: providing a base, a pattern transfer material layer being formed above the base; performing first ion implantation, to dope first ions into the pattern transfer material layer, to form first doped mask layers arranged in a first direction; forming first trenches in the pattern transfer material layer on two sides of the first doped mask layer in a second direction, to expose side walls of the first doped mask layer; forming mask spacers on side walls of the first trenches; performing second ion implantation, to dope second ions into some regions of the pattern transfer material layer that are exposed from the first doped mask layers and the first trenches, to form second doped mask layers; removing the remaining pattern transfer material layer, to form second trenches; and etching the base along the first trenches and the second trenches, to form a target pattern.

Abstract: A method of forming a semiconductor structure includes providing a to-be-etched layer, forming a core layer over the to-be-etched layer, the core layer including a first trench extending along a first direction, forming a sidewall spacer layer on a top surface of the core layer and on sidewalls and a bottom surface of the first trench, forming a block cut structure in the first trench after forming the sidewall spacer layer, and after forming the block cut structure, etching back the sidewall spacer layer until exposing the top surface of the core layer, thereby leaving a sidewall spacer on the sidewalls of the first trench. The block cut structure extends through the first trench along a second direction. The second direction and the first direction are different. The block cut structure includes a first block-cut layer and a second block-cut layer.

Abstract: A semiconductor package structure includes a first redistribution layer, a second redistribution layer and an interconnecting structure. The first redistribution layer has a first surface and a second surface opposite to each other. The second redistribution layer is disposed over the first surface of the first redistribution layer, wherein the second redistribution layer has a third surface and a fourth surface opposite to each other, and the third surface facing the first surface. The interconnecting structure is disposed between and electrically connected to the first redistribution layer and the second redistribution layer, wherein the interconnecting structure comprises a conductive post and a conductive bump stacked to each other.

Abstract: A semiconductor package includes a substrate, a die stack on the substrate, and connection terminals between the substrate and the die stack. The die stack includes a first die having a first active surface facing the substrate, the first die including first through electrodes vertically penetrating the first die, a second die on the first die and having a second active surface, the second die including second through electrodes vertically penetrating the second die, and a third die on the second die and having a third active surface facing the substrate. The second active surface of the second die is in direct contact with one of the first or third active surfaces.

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

Abstract: Contact slots forming method applying photoresists include the following steps. A dielectric layer and a hard mask layer are formed on a substrate sequentially. A first patterned photoresist layer is formed over the hard mask layer, wherein the first patterned photoresist layer includes island patterns connecting to each other by connecting dummy parts. The hard mask layer is etched using the first patterned photoresist layer to form a patterned hard mask layer including island patterns connecting to each other by connecting dummy parts. A second patterned photoresist layer is formed over the patterned hard mask layer. The dielectric layer is etched using the second patterned photoresist layer and the patterned hard mask layer as a mask to form contact holes in the dielectric layer.