Abstract: According to one embodiment, a content addressable memory (CAM) device (100) may include a number of segments (102 or 104). Search target compare circuits (110 and 112) can compare a target value TARGET to programmable information values (PIV0 and PIV1) associated with a particular segment (102 and 104). If a search target value TARGET matches a programmable information value (PIV0 and PIV1), search operations may be performed in a segment (102 or 104). If a search target value TARGET does not match a programmable information value, (PIV0 and PIV1), search operations may be prevented within a segment (102 or 104).

Abstract: A method and apparatus for connecting the processor array of an MPP array to a memory such that data conversion by software is not necessary, and the data can be directly stored in either a normal mode or vertical mode in the memory is disclosed. A connection circuit is provided in which multiple PEs share their connections to multiple data bits in the memory array. Each PE is associated with a plurality of memory buffer registers, which stores data read from (or to be written to) one or two memory data bits. In horizontal (normal) mode connection the memory bits are selected so that all the bits of a given byte are stored in the same PE, i.e., each set of buffer registers associated with a respective PE contains one byte as seen by an external device. In vertical (bit serial) mode, each set of buffer registers contains the successive bits at successive locations in the memory corresponding to that PEs position in the memory word.

Abstract: The present invention relates to a cache memory management system suitable for use with snapshot applications. The system includes a cache directory including a hash table, hash table elements, cache line descriptors, and cache line functional pointers, and a cache manager running a hashing function that converts a request for data from an application to an index to a first hash table pointer in the hash table. The first hash table pointer in turn points to a first hash table element in a linked list of hash table elements where one of the hash table elements of the linked list of hash table elements points to a first cache line descriptor in the cache directory and a cache memory including a plurality of cache lines, wherein the first cache line descriptor has a one-to-one association with a first cache line.

Abstract: This invention is directed to a system and method for caching directory data in a networked computer environment. More particularly, this invention is directed to a system and method for caching directory data in a networked computer environment using a lightweight directory access protocol server to retrieve the selected directory data and caching the selected directory data in a directory cache.

Abstract: A method, apparatus and data structure for managing data in a memory device. The memory device is divided into two volumes. The first volume is intended for storing relatively static data, i.e. data which does not change or is not rewritten frequently. The second volume is intended for storing dynamic data, i.e. data which is changed or rewritten frequently. Each of the volumes is divided into a number of blocks, for example erase blocks, with each block being divided into sectors. In the dynamic volume, each of the erase blocks has one sector allocated for storing metadata, and the remaining sectors in the erase block are available for storing data, other than metadata. In the static volume, each of erase blocks can store more than one sector of metadata, in addition to data other than metadata. The metadata may be stored in consecutive sectors in the erase blocks.

Abstract: An information processing system includes a first processor having a first local memory, a second processor having a second local memory, and a third processor having a third local memory. The system further includes a unit which maps one of the second and third local memories in part of an effective address space of a first thread to be executed by the first processor. The mapped one of the second and third local memories is the local memory of a corresponding one of the second and third processors, which executes a second thread interacting with the first thread. The system also includes a unit that changes a local memory to be mapped in part of the effective address space of the first thread from the one of the second and third local memories to the other.

Abstract: A memory utilizes a data refresh algorithm to preserve data integrity over disturbances caused by memory programming or erase operations. The memory device maintains a counter for each memory block or sector. When a memory block or sector is erased or programmed, the associated counter is set to a predetermined value while other counters are incremented or decremented. Whenever a counter reaches a predetermined threshold value, the associated block or sector is refreshed. The threshold value is set to ensure that each block or sector is refreshed before data integrity is adversely affected by disturbances caused by repeated programming and erase operations.

Abstract: A method for managing storage devices provides a function of automatically changing a scenario and automatically making a partial change to the scenario according to a change in the environment, which are made possible by executing an operation procedure according to an operation rule for storage devices and feeding back a result of execution of the scenario. A storage managing server contains a policy definition file, a scenario definition file, a priority definition file, an execution result value file, a feedback definition file, and a scenario parameter definition file, and also obtains performance information and executes scenarios. By using all those files and processes, the storage managing server implements automatic management of a policy-based storage system.

Abstract: In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuit 3 writes a fail value to a neighbor cell buffer 5 when all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer 5. The control circuit 3 verifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.

Abstract: A system and method for electronic storage of data objects, including at least a first, designated foreground data storage device and at least a second, designated background data storage device, the data storage devices being connectable by way of at least one releasable connection, and an interface engine adapted to manage the transfer of data objects to and from the devices and also between at least two of the devices when the at least two devices are connected to each other, and to generate a logical stack of all the data objects stored in the system, including an index list of identifiers relating to the data objects, the index list being visible from any one of the designated data storage devices whether connected to another designated data storage device or not.

Abstract: The disclosure describes implementations for accessing in parallel a plurality of banks across a plurality of DRAM devices. These implementations are suited for operation within a parallel packet processor. A data word in partitioned into data segments which are stored in the plurality of banks in accordance with an access scheme that hides pre-charging of rows behind data transfers. A storage distribution control module is communicatively coupled to a memory comprising a plurality of storage request queues, and a retrieval control module is communicatively coupled to a memory comprising a plurality of retrieval request queues. In one example, each request queue may be implemented as a first-in-first-out (FIFO) memory buffer. The plurality of storage request queues are subdivided into sets as are the plurality of retrieval queues. Each is set is associated with a respective DRAM device.

Abstract: A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to receive, store and transfer data packets to and from a first and second set of memory chips. Transfer of an internal packet data from the control device to memory takes place such that a first record is stored in a second set of memory chips and additional records are stored in the first set of memory chips. In preferred embodiments, data is allocated in the second set of memory chips such that at least one additional transfer step takes place to the second set of memory chips compared with transfers to the first set of memory chips. In the additional transfer step(s), the first set of memory chips is masked from receiving data.

Abstract: Systems, methods, apparatus and software can be implemented to detect memory leaks with relatively high confidence. By analyzing memory blocks stored in a memory, implicit and/or explicit contingency chains can be obtained. Analysis of these contingency chains identifies potential memory leaks, and subsequent verification confirms whether the potential memory leaks are memory leaks.

Abstract: A system and method are disclosed for providing an enhanced snapshot copy pointer. A data element is stored in a first storage subsystem in the data processing system. A first pointer is created in a pointer table in the first storage subsystem. The first pointer includes an address of the data element. A second pointer is created in the pointer table in the first storage subsystem. The second pointer includes an address of the first pointer.

Abstract: In a virtualization system, physical volumes are virtualized between servers and storage systems such that even when high-performance functions including a remote copy are provided, a virtualization unit does not become a bottleneck of processing. For this purpose, a virtualization node to conduct virtualization includes at least one virtualization switch which receives data from a server and converts the data into data for a real volume to send the data to an associated storage and which receives data from a storage and converts the data into data from a virtualized volume to send the data to a server and at least one virtualization server which receives data requiring processing such as a remote copy from the virtualization switch, performs a particular processing for the data, and then transmits the data via the switch to a server or a storage.

Abstract: A low memory manager configured to cause part of the memory allocated to a specialized application to be held in reserve so that it can be used to support the specialized application during an occurrence of low memory, thus providing time for data backup or remedial steps to be carried out before the affected application crashes.

Abstract: Provided are a method, system and program for prefetching data into cache. A prefetch command is processed that indicates at least one conditional statement and at least one block to prefetch from storage to cache in response to determining that the conditional statement is satisfied.

Abstract: An EV priority switch is configured to allow a user to request a change between an EV priority mode and an HV mode. If an SOC of a power storage device is less than a first threshold value when the change to the HV mode is requested from the EV priority switch during the EV priority mode, an ECU changes the running mode to attain the HV mode and controls the SOC to be close to the SOC at the moment of a request for the change to the HV mode. If the SOC is greater than or equal to the first threshold value, the ECU maintains the EV priority mode. If the SOC reaches a second threshold value less than the first threshold value, the ECU forcefully changes the running mode to attain the HV mode.

Abstract: A method of transmitting/receiving digital contents and an apparatus for receiving the digital contents are disclosed. In a system connected with an Internet protocol (IP) network, service event information may be included in a service discovery record and transmitted/received. Accordingly, the apparatus for receiving the digital contents can receive a service using the service event information in a service discovery step when receiving the service including the digital contents. Since the service event information can be processed independence of the digital contents included in the service, the service can be rapidly provided and unnecessary service event information does not need to be parsed.

Abstract: A multi-channel transceiver includes a phase-locked loop circuit, a first transmitting channel and a second transmitting channel. The phase-locked loop circuit generates a first clock signal set and a second clock signal set with different frequencies. The first transmitting channel includes a first phase adjusting circuit and a first transmitter. The first phase adjusting circuit receives the first clock signal set and generates a first spread spectrum clock signal with a first SSCG profile. According to the first spread spectrum clock signal, the first transmitter generates a first serial data. The second transmitting channel includes a second phase adjusting circuit and a second transmitter. The second phase adjusting circuit receives the second clock signal set and generates a second spread spectrum clock signal with a second SSCG profile. According to the second spread spectrum clock signal, the second transmitter generates a second serial data.