Abstract: An SDRAM and method for operating it provide for increased data access speed. The SDRAM includes a central memory region with memory blocks arranged in sets on respective opposite sides. A plurality of primary sense amplifier sets are provided, each set being associated with a respective pair of the memory blocks and located adjacent thereto. A row cache is provided in the central memory region, and row decoders decode a row address in response to a “bank activate” command and move data from a decoded row address into a primary sense amplifier set associated with a memory block containing the decoded row address and into the row cache, prior to application of a “read” command to the SDRAM. Column decoders decode a column address in response to a “read” command and for reading data from the cache in accordance with the decoded column address.

Abstract: An apparatus and method for loading data values from a memory system are provided. The data processing apparatus comprises a data processing unit operable to execute instructions, and a register file having a plurality of registers operable to store data values accessible by the data processing unit when executing the instructions. Further, a holding register is provided which does not form one of a working set of registers of the register file, and is operable to temporarily store a data value, the holding register having a data portion for storing the data value, and an identifier portion operable to store identifier data associated with the data value.

Abstract: A tape cartridge having dual cartridge memory modules to provide memory redundancy, and a method and apparatus for providing redundancy of cartridge memory information within a tape cartridge. The tape cartridge comprises at least first and second cartridge memory modules, each of which stores an identical set of critical information. Each of the first and second cartridge memory modules includes enough critical information to recover from a failure of either of the cartridge memory modules. The method comprises the steps of providing at least two cartridge memory modules in the tape cartridge, and storing an identical set of critical information in each of the two cartridge memory modules. Each of the two cartridge memory modules includes enough critical information to recover from a failure of either cartridge memory module. In a preferred embodiment, the CM modules are stacked one on top of another and increase the amount of space available for tape directory storage.

Abstract: Methods and systems for data storage are described herein. In one aspect of the invention, an exemplary process includes receiving a first data being directed to a first storage volume, receiving a second data being directed to a second storage volume, writing the first data, as part of a first I/O (input/output) process which begins before a selected time, to a first storage image and a second storage image, the first storage image and the second storage image forming a data mirror prior to the selected time, wherein writes to one image are replicated to the other image, and writing the second data, as part of a second I/O process which begins after the selected time, to the second storage image but not to the first storage image, the second I/O process being capable of running while the first process runs. Other methods and apparatuses are also described.

Abstract: A CAM array which enables a learning process to be an extension of a search process is disclosed. When a search fails to find a matching data in the CAM array, the searched data can automatically be written to a next free address without resorting to any additional search or selection processes.

Abstract: Flash memory in a computing system having blocks that may be read only once per machine reset may be implemented by mapping the flash memory to an address space of the computing system, copying a selected block of at least one of instructions and data from a first region in the flash memory to a second region in a memory of the computing system, at least one of executing the instructions and accessing the data from the second region, unmapping the selected block of flash memory, and overwriting the second region. Subsequent attempts to access the selected block without performing a machine reset will fail. The selected blocks may be used to store secret instructions and/or data.

Abstract: A memory module for a computer system is removably coupled to a computer system mother-board having a data bus and an address bus. The memory module includes a memory interface, a program memory coupled to the memory interface, and a plurality of memory/processing units coupled to the memory interface and the program memory. Each of the memory/processing units includes a system memory and a processor coupled to the respective system memory. Instructions for the processors are transferred to the program memory and stored in the program memory responsive to a first set of addresses on the address bus of the mother-board. The processors then execute the instructions from the program memory, and may access the system memory during execution of the instructions. The system memory may also be accessed through the data bus of the mother-board responsive to a second set of addresses on the address bus of the mother-board.

Abstract: A fault tolerant synchronized virtual memory manager for use in a load sharing environment manages memory allocation, memory mapping, and memory sharing in a first processor, while maintaining synchronization of the memory space of the first processor with the memory space of at least one partner processor. In one embodiment, synchronization is maintained via paging synchronization messages such as a space request message, an allocate memory message, a release memory message, a lock request message, a read header message, a write page message, a sense request message, an allocate read message, an allocate write message, and/or a release pointer message. Paging synchronization facilitates recovery operations without the cost and overhead of prior art fault tolerant systems.

Abstract: A source block (B0) and the logical page number (“8”) of a write target page are identified from the logical address of the write target page. Data objects (DN8, DN9, . . . , DN12) to be written, which a host stores in a page buffer (2), are written into the data areas (DA) of the pages (Q0, Q1, . . . , Q4) of a destination block (Bn), starting from the top page (Q0) in sequence. The logical page number (“8”) of the write target page is written into the redundant area (RA) of the top page (Q0). The physical page number (“6=8?2”) of the write target page is identified, based on the logical page number (“8”) of the write target page and the page offset (“2”) of the source block (B0). When notified by the host of the end of the sending of the data objects (DN8, . . . , DN12), the data items (D13, . . . , D31, D0, D1, . . . , D7) in the source block (B0) are transferred to the pages (Q5, Q6, . . .

Abstract: A content addressable memory (CAM) device is described including a plurality of storage locations, each arranged as a recirculating shift register, and plurality of bit comparators each coupled to a predetermined stage of a respective recirculating shift register for comparing the data contents of the predetermined stage with the data contents of a predetermined stage of a comparand register. The CAM is further coupled to a priority encoder for determining the highest priority match address.

Abstract: A distributed, hierarchically-structured, programmable priority encoder for a content addressable memory (CAM) device including at least one section, the section further including a section level priority encoder, and a plurality of blocks, each block further including a block level priority encoder, and a plurality of slices. The distributed, hierarchically-structured, programmable priority encoder, wherein each slice further including a CAM slice, a maskable comparand register coupled to the CAM slice and a programmable priority encoder coupled to said CAM slice and further coupled to said block level priority encoder.

Abstract: The present invention concerns a data updating method for a non-volatile memory broken down into a plurality of similar memory subdivisions that can be erased independently of each other and among which at least two memory subdivisions (SRA, SRB) are reserved for updating data contained in each of said subdivisions (SM). The method implemented enables the execution time of an update to be reduced by simultaneously erasing the non-reserved memory subdivision (SM) to be updated and an unused reserved memory subdivision (SRB).

Abstract: A caching system includes a caching profile that records a file identifier and an entry time for each file that enters the caching system, and a predictive modeling engine that analyzes the profile to determine metrics for members of a set of caching algorithms. The metrics may be measures of clustering or scattering of the file identities entering the caching system. The algorithm with the most favorable metric is selected as the preferred caching algorithm, and the file is processed according to the preferred algorithm. In one embodiment of the invention, the set of caching algorithms includes a most-used caching algorithm, a least-used caching algorithm, a most-recently-used caching algorithm, and a least-recently-used caching algorithm.

Abstract: A method for reorganizing data in a storage device for improved performance is provided where the device stores data as data units each associated with a sequential address. The method for reorganizing data includes allocating a reorganization region capable of storing N units and grouping the data units into a plurality of extents each having a generally large number of units. The method further includes sorting the extents based on the frequency of request of the units in the extents and copying N most frequently requested units from the sorted extents into the reorganization region while preserving the order of the sorted extents and the order of the sequential addresses of the units in each extent. The method also includes servicing requests for data using data in the reorganization region.

Abstract: The invention is used in a virtual machine monitor for a multiprocessing system that includes a virtual memory system. During a software-based processing of a guest instruction, including translating or interpreting a guest instruction, mappings between virtual addresses and physical addresses are retained in memory until processing of the guest instruction is completed. The retained mappings may be cleared after each guest instruction has been processed, or after multiple guest instructions have been processed. Information may also be stored to indicate that an attempt to map a virtual address to a physical address was not successful. The invention may be extended beyond virtual machine monitors to other systems involving the software-based processing of instructions, and beyond multiprocessing systems to other systems involving concurrent access to virtual memory management data.

Abstract: Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g., array address and row address) of a highest priority matching entry within the entire CAM device. A priority resolution circuit may also resolve competing hard priorities between two or more active hit signals having equivalent soft priority.

Abstract: Systems and methods for selecting pin functionality in memory controllers are provided. These memory controllers have pins that can be used to drive different types of signals, depending on the type of memory coupled to the memory controller. For example, pins can be used to drive clock signals or chip select signals. Accordingly, because different types of memory require different numbers of clock and chip select signals, the same memory controller can be advantageously used with different types of memory. Moreover, memory controller pins that would ordinarily go unused with some types of memory can now be used to increase the number of such memories that can be coupled to the memory controller.

Abstract: There is provided a method for aligning and inserting data elements into a memory based upon an instruction sequence consisting of one or more alignment instructions and a single store instruction. Given a data item that includes a data element to be stored, the method includes the step of aligning the data element in another memory with respect to a predetermined position in the memory, in response to the one or more alignment instructions. A mask is dynamically generated to enable writing of memory bit lines that correspond to the aligned data element. The memory bit lines are written to the memory under a control of the mask. The generating and writing steps are performed in response to the single store instruction.

Abstract: A data storage system that is adapted for storing image data in digital cameras comprises a temporary data storage circuit coupled, in use, to receive image data from the camera, and a permanent data storage circuit coupled, in use, to receive image data from the temporary data storage circuit. A control circuit is coupled to the temporary data storage circuit and the permanent data storage circuit to effect transfer of image data from the temporary data storage circuit to the permanent data storage circuit upon occurrence of a predetermined event. The permanent data storage circuit may be in the form of a write-once non-volatile memory module, which is replaceable in the storage system. The temporary data storage circuit can be a RAM or Flash memory that temporarily stores a image data from the camera when a picture is taken. Then, the user may review the picture before it is permanently stored upon the occurrence of the predetermined event.

Abstract: A method includes storing data in one of a plurality of memory slots in a queue. Each memory slot is associated with a plurality of flags. The method also includes toggling a first of the flags associated with the slot. The method further includes retrieving the data from the memory slot. In addition, the method includes toggling a second of the flags associated with the slot.