Patents Examined by Woo H. Choi
  • Patent number: 7275135
    Abstract: An apparatus and method to de-allocate data in a cache memory is disclosed. Using a clock that has a predetermined number of periods, the invention provides a usage timeframe information to approximate the usage information. The de-allocation decisions can then be made based on the usage timeframe information.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: September 25, 2007
    Assignee: Intel Corporation
    Inventor: Richard L. Coulson
  • Patent number: 7260676
    Abstract: An object of the present invention is to reduce the time a host computer requires to recognize a recordable disc such as CD-R/CD-RW. The method includes the steps of determining whether or not an optical disc loaded in the optical disc recording/reproduction apparatus is an optical disc onto which data is likely to be written (S46), and if the preceding step S46 determines the loaded disc as an optical disc onto which data is likely to be written, acquisition of disc information required for recording on the optical disc is performed by the host computer inter-relatedly with a spinup in the same step (S47). Thus, the optical disc recording/reproducing apparatus returns the disc information to the host computer in step (S4E) without performing the step (S4D) for acquiring the disc information after the completion of the spinup (S4A) for the optical disc onto which data is likely to be written. Thus, the time required for recognizing a recordable disc can be reduced when the disc is loaded.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: August 21, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tsuyoshi Yokokawa
  • Patent number: 7251705
    Abstract: An application-specific embeddable flash memory having three content-specific I/O ports and delivering a peak read throughput of 1.2 GB/s. The memory is combined with a special automatic programming gate voltage ramp generator circuit having a programming rate of 1 Mbyte/s for non-volatile storage of code, data, and embedded FPGA bit stream configurations. The test chip uses a NOR-type 0.18 ?m flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 ?m2.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: July 31, 2007
    Assignee: STMicroelectronics S.r.l.
    Inventors: Marco Pasotti, Michele Borgatti, Pier Luigi Rolandi
  • Patent number: 7249230
    Abstract: According to some embodiments, a queue structure includes a validity vector and an order array.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: July 24, 2007
    Assignee: Intel Corporation
    Inventor: Lim Soon Chieh
  • Patent number: 7243203
    Abstract: The embodiments herein describe a memory device and method for reading and writing data. In one embodiment, a memory device is provided comprising a memory array and first and second data buffers in communication with the memory array. The second data buffer comprises a larger storage capacity than the first data buffer. During a write operation, data is stored in the second data buffer and then stored in the memory array. During a read operation, data is read from the memory array and then stored in the first data buffer but not in the second data buffer. Because the smaller-storage-capacity buffer takes less time to fill than the larger-storage-capacity buffer, there is less of a delay in outputting data from the memory device as compared to memory devices that use a larger-storage-capacity buffer for both read and write operations. Other embodiments are provided, and each of the embodiments can be used alone or in combination with one another.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: July 10, 2007
    Assignee: SanDisk 3D LLC
    Inventor: Roy E. Scheuerlein
  • Patent number: 7237074
    Abstract: Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: June 26, 2007
    Assignee: Sandisk Corporation
    Inventors: Daniel C. Guterman, Stephen J. Gross, Shahzad Khalid, Geoffrey S. Gongwer
  • Patent number: 7234020
    Abstract: In case a fault has occurred in a volume, it was so far difficult to correctly notify a fault by using a host computer which can access the volumes managed by a management computer that integrally manages a plurality of devices constituting a network. The management program of the invention is executed by the management computer connected to computers and to a plurality of storage devices for managing the volumes connected to the computers through a SAN (storage area network). The management program executes a procedure for receiving a notice of fault in the volume from the storage devices, a procedure for receiving volume access control information from a plurality of storage devices for specifying the computers that can access the volumes, and a procedure for notifying the fault in the volume to the computers that are permitted to access the volumes based on the volume access control information.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: June 19, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Etsutaro Akagawa, Hiroshi Furukawa
  • Patent number: 7234030
    Abstract: A scheduler for a set of data packet storage devices (e.g., FIFOs) implements a scheduling algorithm embodied in a look-up table (LUT) that identifies the next FIFO to select for service based on the current status of the FIFOs. In one embodiment, in addition to a memory device used to store the LUT, the scheduler has (1) a latch adapted to store and forward the LUT output and (2) an extractor that implements a finite state machine that determines (1) when to enable the latch and (2) when to forward the identification of the next FIFO to select for service to the set of FIFOs. Using a LUT enables relatively complicated scheduling algorithms to be implemented for relatively large numbers of FIFOs without significantly increasing the execution time of the scheduler.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: June 19, 2007
    Assignee: Lattice Semiconductor Corporation
    Inventors: Navdhish Gupta, Gary D. Allen
  • Patent number: 7231504
    Abstract: A method, system, and program for dynamic memory management of unallocated memory in a logical partitioned data processing system. A logical partitioned data processing system typically includes multiple memory units, processors, I/O adapters, and other resources enabled for allocation to multiple logical partitions. A partition manager operating within the data processing system manages allocation of the resources to each logical partition. In particular, the partition manager manages allocation of a first portion of the multiple memory units to at least one logical partition. In addition, the partition manager manages a memory pool of unallocated memory from among the multiple memory units. Responsive to receiving a request for a memory loan from one of the allocated logical partitions, a second selection of memory units from the memory pool is loaned to the requesting logical partition.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: June 12, 2007
    Assignee: International Business Machines Corporation
    Inventors: Sujatha Kashyap, Mysore Sathyanarayana Srinivas
  • Patent number: 7225305
    Abstract: A system for controlling asynchronous updates to a register, the system including a generally accessible register that is asynchronously updateable by hardware and software. The system also includes protection logic that is in communication with the register. The protection logic includes circuitry to prevent a hardware update to the register from being overwritten by a software update.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: May 29, 2007
    Assignee: International Business Machines Corporation
    Inventor: Michael Billeci
  • Patent number: 7206914
    Abstract: A non-volatile memory system is presented having a boot code section, wherein the size of the boot code section may be programmably selected. One embodiment of the non-volatile memory system includes a memory array, a logic unit, a control unit, and a program store. The memory array includes multiple non-volatile memory cells (e.g., flash EEPROM cells). The memory array is divided into memory blocks of equal size. A number of the memory blocks are allocated for boot code storage, forming a boot code section of the memory array. The control unit controls storage of data within and retrieval of data from the memory array. The control unit includes a configuration register having a boot code section size field. The contents of the boot code section size field determine the number of memory blocks making up the boot code section. The logic unit is coupled between the control unit and the memory array, and receives address, data, and control signals from an external source.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: April 17, 2007
    Assignee: Spansion, LLC
    Inventor: Michael T. Wisor
  • Patent number: 7191290
    Abstract: In one embodiment, a method of processing data in a network with multiple proxy caches, includes: pushing cached data in a first proxy cache to at least one other proxy cache in a cluster configuration; caching the data from the first proxy cache; and permitting a client to access the data in the at least one other proxy cache in the cluster configuration. In another embodiment, a method of processing data in a network with multiple proxy caches, includes: providing a snapshot replica from a first server to second server; and permitting a proxy cache to access the second server for data in the snapshot replica, in response to a disconnect operation of the first server.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: March 13, 2007
    Assignee: Network Appliance, Inc.
    Inventors: Emmanuel Ackaouy, Matthew B. Amdur, Ashish Prakash, Kartik Ayyar
  • Patent number: 7191305
    Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: March 13, 2007
    Assignee: International Business Machines Corporation
    Inventors: William D. Corti, Joseph O. Marsh, Michael Won
  • Patent number: 7185160
    Abstract: To make content irreproducible in a recording device after a set expiration time, the recording device has a read/write unit for reading and writing data on a recording unit, the read/write unit having electric power supplied from an external power source, a clock containing a built-in battery, an input/output interface for inputting data from outside and outputting data to outside, and a controller for controlling the read/write unit and the input/output interface. The recording medium includes an ordinary data area for writing ordinary data and an expiration time data area for writing an expiration time of ordinary data. The controller prevents ordinary data written in the ordinary data area from being output to outside when the expiration time written in the expiration time area has passed a time limit calculated by the clock.
    Type: Grant
    Filed: May 13, 2004
    Date of Patent: February 27, 2007
    Assignee: Hitachi, Ltd.
    Inventor: Takayuki Yamamoto
  • Patent number: 7159081
    Abstract: A method for managing storage devices provides a function of automatically changing a scenario and automatically making a partial change to the scenario according to a change in the environment, which are made possible by executing an operation procedure according to an operation rule for storage devices and feeding back a result of execution of the scenario. A storage managing server contains a policy definition file, a scenario definition file, a priority definition file, an execution result value file, a feedback definition file, and a scenario parameter definition file, and also obtains performance information and executes scenarios. By using all those files and processes, the storage managing server implements automatic management of a policy-based storage system.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: January 2, 2007
    Assignee: Hitachi, Ltd.
    Inventor: Masao Suzuki
  • Patent number: 7155565
    Abstract: A CAM array which enables a learning process to be an extension of a search process is disclosed. When a search fails to find a matching data in the CAM array, the searched data can automatically be written to a next free address without resorting to any additional search or selection processes.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: December 26, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Alon Regev
  • Patent number: 7133977
    Abstract: A system and method for object rundown protection that scales with the number of processors in a shared-memory computer system is disclosed. In an embodiment of the present invention, prior to object rundown, a cache-aware reference count data structure is used to prevent cache-pinging that would otherwise result from data sharing across processors in a multiprocessor computer system. In this data structure, a counter of positive references and negative dereferences, aligned on a particular cache line, is maintained for each processor. When an object is to be destroyed, a rundown wait process is begun, during which new references on the object are prohibited, and the total number of outstanding references is added to an on-stack global counter. Destruction is delayed until the global reference count is reduced to zero.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: November 7, 2006
    Assignee: Microsoft Corporation
    Inventors: Ravisankar Pudipeddi, Neill Clift, Neal R. Christiansen
  • Patent number: 7127556
    Abstract: A method and apparatus for manipulating data in a storage device that is coupled to a host computer. Manipulations that can be performed by the storage device include moving non-contiguous blocks of data between the host computer and the storage device in a single operation. Other manipulations can be performed directly by the storage device without passing data to or from the host computer and include copying data from one logical object that is defined on the host computer to another, initializing, backing-up, transforming, or securely deleting a logical object that is defined by the host computer with a single command. In one embodiment, an application programming interface is provided that allows a relationship between logical objects on a host computer and storage locations on a storage device to be communicated between the host computer and the storage device.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: October 24, 2006
    Assignee: EMC Corporation
    Inventors: Steven M. Blumenau, Philip E. Tamer, Natan Vishlitzky
  • Patent number: 7124243
    Abstract: The present invention relates to a cache memory management system suitable for use with snapshot applications. The system includes a cache directory including a hash table, hash table elements, cache line descriptors, and cache line functional pointers, and a cache manager running a hashing function that converts a request for data from an application to an index to a first hash table pointer in the hash table. The first hash table pointer in turn points to a first hash table element in a linked list of hash table elements where one of the hash table elements of the linked list of hash table elements points to a first cache line descriptor in the cache directory and a cache memory including a plurality of cache lines, wherein the first cache line descriptor has a one-to-one association with a first cache line.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: October 17, 2006
    Assignee: Pillar Data Systems, Inc.
    Inventors: David Alan Burton, Noel Simen Otterness
  • Patent number: 7124238
    Abstract: A USB flash memory device connected to a USB bus includes a flash memory module including at least one flash memory, a USB connector for transferring data packets onto the USB bus and receiving the data packets from the USB bus, a USB controller for controlling the USB connector according to the data packets and for controlling storage of data in and retrieval of data from the flash memory module, a display controller for storing memory storage capacity information of the flash memory module in a usage display register, a display window for displaying a value that is based on the content of the usage display register, and a power unit for supplying a power to the USB flash memory device. The USB connector is configured to be coupled to the USB bus. The USB flash memory device further includes a folding portion which is proximal to the USB connector and enables the USB flash memory device to be folded.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: October 17, 2006
    Assignee: Samsung Electronics, Co., Ltd.
    Inventor: Si-Hoon Hong