Abstract: An on-chip copy command is detected. The on-chip copy command comprises a source address referencing a plane of a memory device, and a destination address referencing the plane. A read verify relevance is estimated by processing, by a machine learning mode, one or more parameters associated with data stored at the source address. Responsive to determining that the read verify relevance satisfies a threshold condition, the on-chip copy command is performed.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a word line connected to the plurality of memory cells, a plurality of bit lines connected respectively to the plurality of memory cells, a sense amplifier connected to the plurality of bit lines, and a controller configured to execute a write operation in a plurality of program loops each including a program operation and a verify operation. The sense amplifier is configured to apply a first voltage, a second voltage higher than the first voltage, a third voltage higher than the second voltage, and a fourth voltage higher than the third voltage to first, second, third, and fourth bit lines of the plurality of bit lines, respectively, while a program voltage is applied to the word line in the program operation.

Abstract: A memory system includes a nonvolatile memory, a controller configured to control the nonvolatile memory, a power supply circuit that is connected to the controller and configured to generate a power supply voltage for the nonvolatile memory and the controller from a voltage supplied from at least one external power supply, and a power storage device that is connected to the power supply circuit and configured to charge to a first energy from a charging voltage supplied by the power supply circuit, and an energy sharing pin that is connected to the power supply circuit and the power storage device, and is connectable to an external power storage device in an external memory system.

Abstract: A read signal generator generates read signals to control read operations of a memory array. The read signal generator can be selectively controlled to generate an oscillating signal having a period that corresponds to a feature one of the read signals. The oscillating signal is passed to a frequency divider that divides the oscillating signal and provides the divided oscillating signal to an output pad. The frequency of the oscillating signal can be measured at the output pad. The frequency of the oscillating signal, and the duration of the read signal feature can be calculated from the frequency of the oscillating signal. The read signal feature can then be adjusted if needed.

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

Abstract: A method of operating a semiconductor memory device includes starting a program operation on selected memory cells using a main verification voltage and an auxiliary verification voltage in response to a program command, receiving a program suspend command during the program operation, and changing at least one auxiliary voltage verification result information among threshold voltage states which are not program-passed to at least one data pattern among threshold voltage states which program-passed, in response to the program suspend command.

Abstract: A read-write conversion circuit includes: a read-write conversion module, performing a read-write operation in response to a read-write control signal to implement data transmission between each of a local data line, a local complementary data line, and a global data line, data signals of the local data line and data signals of the local complementary data line being opposite in phase during the read-write operation, and a control module, outputting a variable read-write control signal in response to a read-write speed configuration signal to control a speed of the read-write operation of the read-write conversion module to be variable.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: A memory device comprises a memory cell array and a control circuit. The control circuit applies a pass voltage to each of a selected and unselected word line from a first to second time point whenever a program loop is performed once. Then, the control circuit applies a program voltage to the selected word line and the pass voltage to the unselected word line from the second to third time point, performs a bit line precharge operation from a fourth time point ahead of the first time point to the second time point when a first program loop is performed, and performs the bit line precharge operation from the fourth time point to a fifth time point, which is the same as or ahead of the first time point, when the other program loops are performed.

Abstract: A semiconductor memory device includes a semiconductor layer, a gate electrode, a gate insulating film disposed therebetween, first and second wirings connected to the semiconductor layer, and a third wiring connected to the gate electrode and is configured to execute a write operation, an erase operation, and a read operation. In the write operation, a write voltage of a first polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the erase operation, an erase voltage of a second polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the read operation, the write voltage or a voltage having a larger amplitude than that of the write voltage is supplied between the third wiring and at least one of the first wiring or the second wiring.

Abstract: Upon detecting power loss during the process of programming multi-level cell (MLC) memory in a storage system, the storage system takes steps to prevent data loss. In one example, the controller sends a graceful shutdown command to the memory, in response to which the memory aborts the ongoing programming operation and stores data from data latches associated with unprogrammed memory cells in single-level cell (SLC) memory. The memory can also store data from programmed memory cells in the SLC memory. The data to be programmed in the MLC memory can be reconstructed prior to powering down the storage system or after the storage system is powered back up. The reconstructed data can then be programmed in the MLC memory.

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a power loss event has occurred, determine that one or more blocks are in an erased state, examine a block of the one or more blocks to determine whether the block is a SLC erased block or a TLC erased block, and place the block in a SLC pre-erase heap if the block is the SLC erased block or in a TLC pre-erase heap if the block is the TLC erased block. The controller is further configured to determine a first bit count of page0 for a SLC voltage for the block, determine a second bit count of page1 for a TLC voltage for the block, and classify the block as either a SLC erased block or a TLC erased block.

Abstract: A method includes performing a first write operation that writes data to a first memory unit of a group of memory units in a memory device, determining a write-to-write (W2W) delay based on a time difference between the first write operation and a second write operation on a memory unit in the group of memory units, wherein the second write operation occurred prior to the first write operation, identifying a threshold time criterion that is satisfied by the W2W delay, identifying a first read voltage level associated with the threshold time criterion, and associating the first read voltage level with a second memory unit of the group of memory units. The second memory unit can be associated with a second read voltage level that satisfies a selection criterion based on a comparison of the second read voltage level to the first read voltage level.

Abstract: A semiconductor memory device capable of satisfying multiple reliability conditions and multiple performance requirements is provided. A variable resistance memory of the disclosure makes it possible to write data in a memory array by changing a write condition according to the type of a write command from the outside. If the write command is an endurance-related command, an endurance algorithm is selected and data is written in an endurance storage area. If the write command is a retention-related command, a retention algorithm is selected and data is written in a retention storage area.

Abstract: An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.

Abstract: A storage device can reorganize a sequentially performed calibration task and delegate various steps of the task to multiple memory planes. By utilizing a characteristic that provides for similar memory device responses across multiple planes, the calibration task processed on one memory plane can be applied to another memory plane within the device. In this way, partial calibration data may be generated across a plurality of memory planes, and subsequently pooled together to generate a unified calibration data that can be utilized on each of the plurality of planes to do a full calibrated read on memory devices, thus reducing the amount of time needed to perform a calibrated read. Reduced times for calibrated reads allows for increased resolution of threshold valley scans, increased lifespan of the storage device, improved read times, and also provides for data write methods to use less memory during intermediate multi-pass programming steps.

Abstract: The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing in a dummy row of said memory block at least a known pattern; performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly; adopting the trimming parameters of the correct reading for the subsequent reading phases. The disclosure further relates to a memory device structured for implementing the above method.

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: A memory device can include a nonvolatile memory (NVM) cell array, data path circuits, coupled between the NVM cell array and an output of the device, that are configured to enable access to the NVM cell array via a plurality of bit lines. A first charge pump can generate a first voltage supply. A second charge pump can generate a second voltage supply. Switch circuits are configured to, in a first mode, couple the first voltage supply to data path circuits, and in a second mode, couple the second voltage supply to the data path circuits. The first charge pump, the second charge pump, the switch circuits, the data path circuits and the NVM cell array are formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.