Abstract: Systems and methods are disclosed, including moving host data stored in volatile memory of the storage system to non-volatile memory of the storage system and transitioning a storage system power status of a unidirectional power state signal interface from an active power status to a low power status.

Abstract: An Ethernet communication device includes a data interface and circuitry. The data interface is configured for communicating with a neighbor device. The circuitry is configured to exchange Ethernet data frames with the neighbor device over the data interface, wherein successive data frames are separated in time by an Inter-Packet Gap (IPG) having at least a predefined minimal duration, and to further exchange with the neighbor device, over the data interface, during the IPG between Ethernet frames exchanged on the data interface, a wake-up/sleep command that instructs switching between an active mode and a sleep mode.

Abstract: A controllable voltage source (902) is coupled to a microelectronic circuit (901) for providing an operating voltage. Said microelectronic circuit (901) is adaptive, so its performance is at least partly configurable by value of said operating voltage. The operating voltage is regulated into conformity with a target value. Reregulating said operating voltage into conformity with a new target value involves a time constant. On a processing path a first register circuit (502) comprises a data input coupled to an output of a preceding first logic unit (501). The microelectronic circuit (901) responds to a digital value at said data input changing later than an allowable time limit by generating a timing event observation (TEO) signal. The allowable time limit is defined by at least one triggering edge of at least one triggering signal coupled to the first register circuit (502). The system uses said TEO signal to trigger an increase in said operating voltage faster than said time constant.

Abstract: A multiphase power supply including a controller and phases can respond to a drop in load level by reducing all but one active phase to reduce power consumption. If the load level drops further, further reduction of the power consumption could be achieved by reducing, changing, or disabling the functions of some circuits within the active phase during these conditions. Estimating these conditions, however, may be difficult for a controller when the communication between the controller and the phase is limited. The disclosure describes an active phase that estimates a state of the load based on a sensed output current and a pulse width modulation control signal. The active phase may change its operating mode to match the estimated state of the load so that lighter load conditions consume less power. Furthermore, the idle phase(s) may nearly turn off all function except PWM detection to save power. Because this mode change is local to the phase, no additional communication with the controller is required.

Abstract: To individually control supply of the power supply voltage to circuits, a semiconductor device includes a CPU, a memory that reads and writes data used in arithmetic operation of the CPU, a signal processing circuit that generates an output signal by converting a data signal generated by the arithmetic operation of the CPU, a first power supply control switch that controls supply of the power supply voltage to the CPU, a second power supply control switch that controls supply of the power supply voltage to the memory, a third power supply control switch that controls supply of the power supply voltage to the signal processing circuit, and a controller that at least has a function of controlling the first to third power supply control switches individually in accordance with an input signal and instruction signals input from the CPU and the signal processing circuit.

Abstract: Technologies for managing Function-as-a-Service function requests based on thermal and power awareness include an edge entity device having a circuitry to receive, from an edge device, a request to execute a function in an edge network environment having a plurality of edge entities. The circuitry is also to evaluate thermal and power criteria associated with the request and determine, as a function of a predicted thermal output over a specified time period relative to thermal and power criteria, whether to execute the function. In response to a determination by the circuitry to not execute the function, the circuitry is to select an edge entity of a plurality of edge entities that is able to satisfy the thermal and power criteria. The circuitry is further to forward the request to the selected edge entity.

Abstract: Temporary firmware is provided as cloud services. Different temporary firmware containers are downloaded via a communications network. A light-weight operating system launches and executes the temporary firmware containers during a boot operation, POST operation, or other scheme. The temporary firmware containers thus detect and perhaps resolve POST errors. The light-weight operating system may also download a full-service/resource operating system. A second or subsequent boot operation may be performed, but control is ceded to the full-service/resource operating system. Multiple firmware tenants may thus be temporarily downloaded to a bare metal machine to support POST error detection activities. Advanced OS serviceability, diagnostics, and other containerized firmware may thus be quickly and simply launched without requiring the excessive time and difficulties of using the full-service/resource operating system.

Abstract: An operating device of a cross-power domain multiprocessor and a communication method thereof. The device includes: at least two processors, wherein each is connected with a processor channel connected with a memory, and the processor channel includes read and write channels; the memory and an interface parsing unit for controlling the processor channels; the memory includes a shared memory unit and a dedicated memory of each processor; a memory allocation unit for allocating the shared memory and a detection wake-up unit for detecting a processor state and receiving a data transmission command. When the processor with a receiving end in a dormant mode is awoken, information can be saved in the shared memory and processed according to the information priority after the processor is completely awake. The shared memory performs dynamic allocation according to the quantity of the wake-up processors, which improves the communication efficiency between the memory and processors.

Abstract: In some embodiments a distributed computing system is provided that includes a plurality of different feature modules and a matching engine. The different feature modules each provide different processing for handling parent requests and submitting, to the matching engine, commands for child data transaction requests that are associated with the parent request.

Abstract: Methods and apparatus relating to techniques for repeating graphics render pattern detection are described. In an embodiment, a repeating pattern in a plurality of workload blocks is detected. Information corresponding to the plurality of workload blocks is stored and analyzed to determine a Dynamic Voltage Frequency Scaling (DVFS) sampling window of a processor. Other embodiments are also disclosed and claimed.

Abstract: A clustering device includes: an evaluation score calculation section configured to calculate an evaluation score or evaluation scores for evaluating a classification result; a batch process section configured to classify multiple element data into clusters with an optimum number of clusters, based on the evaluation scores respectively obtained for different number of clusters by assigning each of the multiple element data to one of the clusters; an update process section configured to assign newly added element data to a cluster that is closest to the newly added element data among the clusters into which the multiple element data are classified by the batch process section; and a determination section configured to determine validity of a classification result after assigning the newly added element data to the cluster, based on the evaluation score obtained by assigning the newly added element data to the cluster by the update process section.

Abstract: The present disclosure relates to systems and methods for power outage protection. The system may obtain a read/write signal of each of a plurality of storage devices. For each of the plurality of storage devices, the system may identify a state of the storage device based on the read/write signal of the storage device. The state of the storage device may include a read/write state or an idle state of the storage device. In response to an interruption of power supply to the plurality of storage devices, the system may selectively provide electric power to the plurality of storage devices using a power source based at least partially on the states of the plurality of storage devices.

Abstract: Systems and methods for determining subsystems of a computer environment that are in a mutual independence state can include a computing device obtaining information indicative of a group of assets of a subsystem of a computer environment. For each asset of the group of assets, the computing device can identify one or more first assets on which the asset depends and one or more second assets that depend on the asset, and determine whether the one or more first assets and the one or more second assets belong to the group of assets. The computing device can determine that the subsystem is in a mutual independence state upon determining, for each asset of the group of assets, that the first and second assets belong to the group of assets. The computing device can update a data record to indicate the determined state of subsystem of the computer environment.

Abstract: In one embodiment, the present disclosure includes a method of reducing power in an artificial intelligence processor. For each cycle, over a plurality of cycles, an AI model is translated into operations executable on an artificial intelligence processor. The translating is based on power parameters that correspond to power consumption and performance of the artificial intelligence processor. The AI processor is configured with the executable operations, and input activation data sets are processed. Accordingly, result sets, power consumption data, and performance data are generated and stored over the plurality of cycles. The method further includes training an AI algorithm using the stored parameters, the power consumption data, and the performance data. A trained AI algorithm outputs a plurality of optimized parameters to reduce power consumption of the AI processor. The AI model is then translated into optimized executable operations based on the plurality of optimized parameters.

Abstract: An integrated coprocessor such as an accelerated processing unit (APU) generates commands for execution on a discrete coprocessor such as a discrete graphics processing unit (dGPU). Power distribution circuitry selectively provides power to the APU and the dGPU based on characteristics of workloads executing on the APU and the dGPU and based on a platform power limit that is shared by the APU and the dGPU. In some cases, the power distribution circuitry determines a first power provided to the APU and a second power provided to the dGPU. The power distribution circuitry increases the second power provided to the dGPU in response to a sum of the first and second powers being less than the platform power limit. In some cases, the power distribution circuitry modifies the power provided to the APU, the dGPU, or both in response to changes in temperatures measured by a set of sensors.

Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

Abstract: A non-transitory computer-readable recording medium stores a control program for each of control circuits in an information processing device constituted by a plurality of the control circuits and for causing a computer to execute a process including: when synchronization of power consumption between the respective control circuits is detected, computing delay time of an own control circuit such that the control circuits have the delay time different from each other; disclosing data of the power consumption at a past time point with respect to the delay time, to other control circuits as the data of the current power consumption; and performing load balancing by using the data of the power consumption disclosed to the other control circuits and the data of the power consumption disclosed by the other control circuits.

Abstract: Aspects of the disclosure relate to computer hardware and software for managing a field device (e.g., a transmitter, an actuator, a valve, a switch, a sensor, a power supply, a meter, or the like, used in one or more pieces of equipment that process one or more input chemicals to create one or more products in a chemical plant, a petrochemical plant, a refinery, or the like) by using an interactive automation/self-learning program module installed in a computing device (e.g., a mobile device). Some aspects of the disclosure provide techniques that may enable a computing device to connect to a field device; automatically identify the field device; provide guidance to manage the connected field device; receive input corresponding to the guidance; and/or manage the field device based on the input.

Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.

Abstract: An apparatus and method are provided which take advantage of heterogeneous compute capability to dynamically pick the best operating core for BIOS power-up flows and sleep exit flows (e.g., S3, S4, and/or S5). The selection of the BSP is moved to an early power-up time instead of a fixed hardware selection at any time. For maximum boot performance, the system selects the fastest capable core as the BSP at an early power-up time. In addition, for maximum power saving, the system selects the most power efficient core as the BSP. Processor or switching for selecting the BSP happens during the boot-up as well as power-up flows (e.g., S3, S4, and/or S5 flows).