Abstract: A hardware encryption module with reconfigurable security algorithms for randomly selecting block ciphers, stream ciphers, and their components, for internet of things (IoT) and data security applications. A corresponding system contains a hardware number generator for generating unique secrets in digital and wireless communication protocols. The system contains a cryptographically secure pseudorandom number generator for creating deterministic random sequences for the reconfigurable logic module. The system contains a multiplexing scheme to send keys and cipher texts in accordance with a wireless communication protocol. The hardware encryption module can be used to reconfigure block cipher algorithms, modes of operation, key scheduling algorithms, confusion functions, and/or round orders, based on reconfigurable logic. One type of reconfigurable logic allows stream cipher algorithms and key mixing keys to be changed at random.

Abstract: The versatility of a power feeding device is improved. A power storage system includes a power storage device and a power feeding device. The power storage device includes data for identifying the power storage device. The power storage device includes a power storage unit, a switch that controls whether power from the power feeding device is supplied to the power storage unit, and a control circuit having a function of controlling a conduction state of the switch in accordance with a control signal input from the power feeding device. The power feeding device includes a signal generation circuit having a function of identifying the power storage device by the data input from the power storage device, generating the control signal corresponding to the identified power storage device, and outputting the generated control signal to the power storage device.

Abstract: Certain aspects of the present disclosure provide a method for performing multimode inferencing, comprising: receiving machine learning model input data from a requestor; processing the machine learning model input data with a machine learning model using processing hardware at a first power level to generate first output data; selecting a second power level for the processing hardware based on comparing the first output data to a threshold value; processing the machine learning model input data with the machine learning model using the processing hardware at the second power level to generate second output data; and sending second output data to the requestor.

Abstract: A computer-implemented method, computer program product and computing system for recording video information on the computing device during a monitored event. Execution information is recorded on the computing device during the monitored event. The video information and the execution information are temporally synchronized to form temporally-synchronized diagnostic content.

Abstract: The exemplary embodiments disclose a method, a computer program product, and a computer system for supplying power to a device. The exemplary embodiments may include generating power from movement of one or more metal coils relative to one or more pieces of cloth containing one or more electronic threads and transferring the generated power to a device.

Abstract: Aspects of the present disclosure involve systems and methods for performing operations comprising providing a messaging application comprising a feature to a client device, the feature being implemented by operations having alternative complexity levels, wherein a first complexity level represents a first amount of device resources consumed by a first set of operations, and wherein a second complexity level represents a second amount of device resources consumed by a second set of operations; determining that the first configuration rule is satisfied by a first property of the client device; and in response to determining that the first configuration rule is satisfied by the first property of the client device, causing the feature to be implemented on the client device by the first set of operations having the first complexity level that consume a greater amount of device resources than the second set of operations having the second complexity level.

Abstract: Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.

Abstract: A network system includes a higher-level device, a first intermediate device connected to the higher-level device, and a second intermediate device connected to the higher-level device. The first intermediate device is configured to control supply of an electric power to a first lower-level device via a first device being able to be controlled to interrupt. The second intermediate device is configured to control supply of an electric power to a second lower-level device via a second device being able to be controlled to interrupt, the second lower-level device being a redundant component for the first lower-level device.

Abstract: In a power supplying system, a selection unit that selects one of a first power feed unit and a second power feed unit, a first voltage determination unit that compares a voltage of an output of the first power feed unit with a first threshold value, a second voltage determination unit that compares a voltage of an output of the second power feed unit with a second threshold value, and a management unit that sets the first threshold value and the second threshold value are provided.

Abstract: A chip includes an instruction storage unit, a processor core, an input circuit, a neural network circuit, power-consuming circuits, and a switch circuit. When the chip runs, the processor core performs a processing operation according to the instructions under being supplied with a current. At the same time, the neural network circuit predicts an upcoming change of the current according to data stream, representing the time-varying current, from the input circuit, and outputs a corresponding control signal. The switch circuit selectively provides a clock to one or more power-consuming circuits under the control of the control signal, so that each power-consuming circuit receiving the clock operates under being supplied with the current. Therefore, the chip can predict upcoming requirement of high electricity consumption, and duly start up a current wasting mechanism in advance, to avoid an excessive voltage drop without affecting operation efficiency of the processor core.

Abstract: An accelerating boot time system includes a memory and a processor. The memory is configured to pre-store a boot process to be performed on the first boot. The processor is configured to directly read the boot process from the memory and execute the boot process when the first boot is performed. Also, the processor executes a monitoring process to monitor a plurality of hardware usage rates of the plurality of devices each time the device is powered up, and inserts the hardware usage rates into a machine learning algorithm to determine whether a particular process supported by the devices is abnormal.

Abstract: A basic input/output system provides an interface for a core aggregation layout that identifies a grouping of processor cores into core aggregations, wherein each of the core aggregations is associated with a maximum allowable C-state. A processor may monitor an information handling system during operation of an application to gather data associated with latency sensitivity of the application, update the core aggregation layout based on the data gathered during the operation of the application, and pin a thread for execution to one of the processor cores based on the latency sensitivity of the application and the maximum allowable C-state.

Abstract: A digital control scheme controls an integrator of a PID filter to implement non-linear control of saturating the duty cycle during which the proportional and derivative terms of the PID filter are set to 0 while the integrator and its internal states (previous values or memory) is set to a duty cycle that is the sum of the current nominal duty cycle plus a deltaD. The deltaD is the maximum duty cycle increment that is used to regulate a voltage regulator from ICCmin to ICCmax and is a configuration register that can be set post silicon. An FSM moves from a non-linear all ON state to an open loop duty cycle which maintains the output voltage slightly higher than the required Vref. After a certain period in this open loop, the FSM then ramps down the open loop duty cycle value until the output voltage is close to the Vref.

Abstract: A semiconductor device includes an internal command generation circuit configured to generate a synthesized command from a command which is inputted in synchronization with any one of a first internal clock and a third internal clock generated by dividing a frequency of a clock, and configured to generate a first internal command and a second internal command by delaying the synthesized command depending on a detected input time of the command. The semiconductor device also includes a data transmission circuit configured to generate transmission data from data in synchronization with any one of the first internal command and the second internal command.

Abstract: An embodiment of the present invention is directed to an innovative approach to installing, upgrading and downgrading the package irrespective of the kernel version during system boot time after an operating system (OS) patching kernel update.

Abstract: A convolutional neural network (CNN) operation accelerator comprising a first sub-accelerator and a second sub-accelerator is provided. The first sub-accelerator comprises I units of CNN processor cores, J units of element-wise & quantize processors, and K units of pool and nonlinear function processor. The second sub-accelerator comprises X units of CNN processor cores, Y units of first element-wise & quantize processors, and Z units of pool and nonlinear function processor. The above variables I˜K, X˜Z are all greater than 0, and at least one of the three relations, namely, “I is different from X”, “J is different from Y”, and “K is different from Z”, is satisfied. A to-be-performed CNN operation comprises a first partial CNN operation and a second partial CNN operation. The first sub-accelerator and the second sub-accelerator perform the first partial CNN operation and the second partial CNN operation, respectively.

Abstract: Techniques are described for improving security of a boot sequence of a system, such as an artificial reality system. In some examples, a method includes configuring, by a boot sequencing system, attack detection circuitry based on configuration information accessed from a first storage device; after configuring the attack detection circuitry, starting, by the boot sequencing system, a root of trust processor to initiate a boot sequence; enabling access, by the root of trust processor during the boot sequence, to secret information stored in a second storage device.

Abstract: A temperature control system, adapted to a central processing unit powered by a power supply module of an electronic device, is provided. The temperature control system includes a setting module, a first temperature detecting module, a second temperature detecting module, and a power adjusting module. The setting module is configured to set a target temperature of the CPU and a target temperature of the power supply module. The first temperature detecting module is configured to obtain a detected temperature of the CPU. The second temperature detecting module is electrically connected to the power supply module, to obtain a detected temperature of the power supply module.

Abstract: A closed-loop service, referred to as an Adaptive Data Analytics Service (ADAS), characterizes the performance of a system or systems by providing information describing how users or agents are operating the system, how the system components interact, and how these respond to external influences and factors. The ADAS then builds models and/or defines relationships that can be used to optimize performance and/or to predict the results of changes made to the system(s). Subsequently, this learning provides the basis for administering, maintaining, and/or adjusting the system(s) under study. Measurement can be ongoing, even after the operating parameters or controls of a system under the administration or monitoring of the ADAS have been adjusted, so that the impact of such adjustments can be determined.

Abstract: An information handling system includes a general storage for storing application data of applications hosted by the information handling system. The information handling system also includes a management storage for storing management data used to manage operation of the information handling system. The information handling system further includes a management storage manager that obtains data for storage in the management storage; encrypts the data to obtain encrypted data and authentication data for the encrypted data; generates error correction code data for the encrypted data and the authentication data; and stores, as a new record, the encrypted data, the authentication data, and the error correction code data in the management storage.