Abstract: An apparatus and method are provided which take advantage of heterogeneous compute capability to dynamically pick the best operating core for BIOS power-up flows and sleep exit flows (e.g., S3, S4, and/or S5). The selection of the BSP is moved to an early power-up time instead of a fixed hardware selection at any time. For maximum boot performance, the system selects the fastest capable core as the BSP at an early power-up time. In addition, for maximum power saving, the system selects the most power efficient core as the BSP. Processor or switching for selecting the BSP happens during the boot-up as well as power-up flows (e.g., S3, S4, and/or S5 flows).

Abstract: A user equipment may generate one or more temperature thresholds based on thermal mitigation guidelines. The one or more temperature thresholds may define a first temperature zone and a second temperature zone. The user equipment may detect a temperature of the user equipment. The user equipment may identify whether the temperature occurs in the first temperature zone or the second temperature zone. The user equipment may send information to a network device to cause one or more network actions to be performed. The one or more network actions may be configured to maintain or reduce the temperature within the first temperature zone or to reduce the temperature to cause the temperature to switch from the second temperature zone to the first temperature zone.

Abstract: Systems and methods are disclosed for derivation of executable tasks for synchronizing configuration parameters. An example method may comprise: obtaining a first set of configuration parameters of a first computer system corresponding to a first time value; obtaining a second set of configuration parameters of the first computer system corresponding to a second time value; performing a comparison between the first set of configuration parameters and the second set of configuration parameters to determine one or more differences; deriving in view of the comparison, one or more executable tasks to convert the first set of configuration parameters to the second set of configuration parameters; and providing, to a second computer system, the one or more executable tasks for execution by the second computer system to synchronize configuration parameters of the second computer system to configuration parameters of the first computer system corresponding to the second time value.

Abstract: An image forming apparatus comprises a non-volatile memory storing start-up firmware a volatile memory having a memory space commonly available for the start-up firmware and an operating system of the image forming apparatus; and a control unit configured to copy, to the memory space, a setting value of a setting item for write-protecting the non-volatile memory, among setting items included in the start-up firmware, wherein the operating system acquires and checks the setting value copied to the memory space.

Abstract: Processor-based systems employing configurable local frequency throttling management to manage power demand and consumption, and related methods. For example, such processor-based systems may include a processor and other power circuitry to control power to the processor. The processor includes a clock control circuit that is configured generate a clock signal(s) at a designated frequency to clock a processor core(s) in the processor at a desired operating frequency(ies). The clock control circuit is configured to dynamically throttle (i.e., limit and/or reduce) the frequency(ies) of a clock signal(s) clocking the processor in response to a frequency throttle event that may be an unexpected event. Reducing power demand may be important to ensure that the processor can continue to operate under interrupted or reduced power supply conditions. It may be faster to throttle the operating frequency of a processor than to throttle the operating voltage of power supplied to the processor.

Abstract: A method of initializing an application-specific integrated circuit (ASIC), the method including reading, by a boot microcode engine integrated with the ASIC, microcode from an electrically programmable non-volatile memory (EP-NVM) integrated on a same die as the ASIC. The method further includes writing the microcode onto internal memories of a micro-controller of the ASIC and initializing the micro-controller by the boot microcode engine. The method also includes loading, by the micro-controller, a full boot image from an additional storage device distinct from the EP-NVM onto the internal memories of the micro-controller and initializing the ASIC by the micro-controller based on the full boot image.

Abstract: Embodiments of systems and methods for managing control of a security processor in a supply chain are described. In some embodiments, a security processor may include: a core; and a memory coupled to the core, the memory having program instructions stored thereon that, upon execution by the core, cause the security processor to: store a first public key usable to initiate a first secure boot process and unusable to initiate a second secure boot process; store a second public key usable to initiate the second secure boot process and unusable to initiate the first secure boot process; and in response to a first change of control or ownership of the security processor, render the first public key unusable to initiate the first secure boot process.

Abstract: Methods and apparatus for isolation of sub-system resources (such as clocks, power, and reset) within independent domains. In one embodiment, each sub-system of a system has one or more dedicated power and clock domains that operate independent of other sub-system operation. For example, in an exemplary mobile device with cellular, WLAN and PAN connectivity, each such sub-system is connected to a common memory mapped bus function, yet can operate independently. The disclosed architecture advantageously both satisfies the power consumption limitations of mobile devices, and concurrently provides the benefits of memory mapped connectivity for high bandwidth applications on such mobile devices.

Abstract: An electronic device includes an AI power controller that predicts future load transients within a system and that dynamically alters power settings in anticipation of the predicted future load transients. To predict a future load transients, the AI power controller receives as an input application signature data from an application executing on the device. The application signature data includes at least media frame data generated by the application during a time interval. The AI power controller executes logic to compare the received application signature data to historical application signature data, where the historical application signature data includes media frame data generated by the application during one or more past execution instances of the application. Based on the comparison, the AI power controller predicts a load transient of the application at a future point in time and dynamically adjusts a power control setting of the device in anticipation of the predicted load transient.

Abstract: A system, method, and apparatus are provided for securely controlling operations of a data processing system by activating a security subsystem to control startup behavior of application subsystems, installing SMR parameters which include an initial authenticity proof for use with an initial verification process for the SMR and calculating an alternate authenticity proof for use with a subsequent verification process for the SMR, and then by subsequently verifying the SMR using the alternate authenticity proof for the subsequent verification process applied to the SMR so that the security subsystem can apply a comprehensive system reaction for the application subsystem based on the SMR verification results.

Abstract: An apparatus is disclosed for implementing a multi-mode direct-current (DC)-to-DC power converter. In an example aspect, the apparatus includes a DC-to-DC power converter with a flying capacitor, an inductor, and four switches. The inductor is coupled between a second node and a battery node. A first switch is coupled between a first node and a first terminal of the flying capacitor. A second switch is coupled between the first terminal and the second node. A third switch is coupled between a second terminal of the flying capacitor and the second node. A fourth switch is coupled between the second terminal and a ground node. The DC-to-DC power converter is configured to selectively transfer power from the first node to the battery node according to a first operational mode and transfer other power from the battery node to the first node according to a second operational mode.

Abstract: Techniques and mechanisms for transparently transitioning an interconnect fabric between a first frequency and a second frequency. In an embodiment, the fabric is coupled to an end point device via an asynchronous device. One or more nodes of the fabric operate in a first clock domain based on a clock signal, while the end point device operates in a different clock domain. Controller circuitry changes a frequency of the clock signal by stalling the clock signal throughout a first period of time which is greater than a duration of three cycles of a lower one of the first frequency or the second frequency. After the first period of time, cycling of the clock signal is provided at the second frequency. In another embodiment, the asynchronous device enables the frequency change without preventing communication with the end point device.

Abstract: A compute device of an information handling system includes a security chip. The security chip includes a programmable read only memory, which in turn includes multiple one-time programmable slots and a one-time programmable slot counter. A first slot of the one-time programmable slots stores a first group of keys associated with a first entity of the security chip. A second slot of the one-time programmable slots stores a second group of keys associated with a second entity of the security chip. The one-time programmable slot counter includes multiple entries. Each of the entries is associated with a different one of the one-time programmable slots. Each of the entries is preset to a first value. The one-time programmable slot counter is only able to count in one direction. A first entry of the entries is updated to invalidate the second group of keys associated with the second entity.

Abstract: The invention relates to a power providing device (2) for providing power to a plurality of power receiving devices (31), a power distribution system including such power providing device (2), a method for providing power to a plurality of power receiving devices (31) and a corresponding computer program. During standby the power providing device (2) is beneficially supplied with power coming from a power source (1) dedicated or adjusted for the low energy consumption, e.g. a uplink port (23) or a shared power bus. The current drawn from such power source (1) (or the power provided to the downlink power receiving devices (31)) is measured and, for example, the derivative is used in order detecting a current increase just when it starts. This information may be used such the main power supply (29) gets started in order to be available for more power demand than available through the hierarchical powering coming from the standby power source (1).

Abstract: Examples provide a method and apparatus for a multi-domain computing device providing physical separation of computing domains and network isolation. The multi-domain computing device includes a user facing panel with a shared display device and a keyboard, video mouse (KVM) switch. A set of domain-specific devices which are not shared between domains may include one or more processors, card readers, network devices, headset jacks, and power switches. The devices shared by the different domains include a display screen, power supply, the KVM switch and/or touchscreen. Each domain is configured to power up, boot and operate independently within a single physical unit.

Abstract: An apparatus to facilitate enabling late-binding of security features via configuration security controller for accelerator devices is disclosed. The apparatus includes a security controller to initialize as part of a secure boot and attestation chain of trust; receive configuration data for portions of the security controller, the portions comprising components of the security controller capable of re-programming; verify and validate the configuration data to as originating from a secure and trusted source; and responsive to successful verification and validation of the configuration data, re-program the portions of the security controller based on the configuration data.

Abstract: A power failure monitoring method applied to a programmable logic device includes outputting a power supply enable signal to instruct a power supply to power on, starting a counter, determining whether a first abnormal power status indication signal exists for each power supply before a current reading of the counter reaches a preset value, and in response that the first abnormal power status indication signal exists, outputting a first read notification signal according to the first abnormal power status indication signal, so that a baseboard management controller reads the first abnormal power supply status indication signal according to the first read notification signal and generates a corresponding power status log.

Abstract: The present invention relates to a method and system energy aware scheduling for sensors (Internet of Things (IoT)). More specifically, the method and system relates to energy scheduling of battery powered sensors or sensors powered using energy harvesters such that accurate and up to date information may be received from said sensors and at the same time minimizing the power utilized by said battery powered or energy harvester powered sensors.

Abstract: A method of performing safety-critical rendering at a graphics processing unit within a graphics processing system, the method comprising: receiving, at the graphics processing system, graphical data for safety-critical rendering at the graphics processing unit; scheduling at a safety controller, in accordance with a reset frequency, a plurality of resets of the graphics processing unit; rendering the graphical data at the graphics processing unit; and the safety controller causing the plurality of resets of the graphics processing unit to be performed commensurate with the reset frequency.

Abstract: A BIOS/OS key provisioning system includes an NVMe storage device coupled to a server device via a network. The server device includes an operating system engine and a BIOS engine. Subsequent to a current initialization of the server device and prior to an immediately subsequent initialization of the server device, the BIOS engine retrieves a key from a key storage subsystem and stores the key in a BIOS memory subsystem. When the BIOS engine receives a current key request that identifies the key from the operating system engine and determines that the key stored in the BIOS memory system has not previously been accessed subsequent to the current initialization and prior to the subsequent initialization, it provides the key from the BIOS memory subsystem to the operating system, and prevents the key from being provided from the BIOS memory subsystem in response to any subsequent key request.