Abstract: A device with extensibility includes an architecture modeled as an ability acquisition model including an ability unit for implementing an ability, an data input unit that is an interface for an input from the ability unit, and a data output unit that is an interface for an output from the ability unit, as an architecture for additionally incorporating a new ability to a basic configuration of the device, and includes an ability setting unit for adding the new ability to the device by setting a function to each of the ability unit, the data input unit, and the data output unit, based on ability providing data including ability setting data, input setting data, and output setting data.

Abstract: Examples are disclosed for adaptive graphics subsystem power and performance management including adjusting one or more power management or performance attributes for a graphics subsystem for a computing platform based on a comparison of a current quality metric to a target quality metric. The current and target quality metric to be separately determined based on current and target quality of service (QoS) values for power management and performance for at least portions of the computing platform.

Abstract: An information processing apparatus includes a first circuit configured to operate by receiving a first voltage or a second voltage higher than the first voltage; a second circuit configured to output a signal indicating which of the first voltage or the second voltage is to be input to the first circuit; and a control unit configured to receive the signal output by the second circuit and to output, to the first circuit, a signal indicating a voltage to be supplied to the first circuit. The control unit is configured to output a signal indicating the second voltage for a period until when the signal output by the second circuit has stabilized, and to output a signal indicating a voltage as indicated by the signal received from the second circuit, after the signal output by the second circuit has stabilized.

Abstract: A semiconductor device includes a delay-locked clock generation circuit configured to generate a delay-locked clock which is driven by at least one internal clock selected from a plurality of internal clocks in response to a phase control signal. The semiconductor device also includes a latency command generation circuit configured to generate a latency command for generating transmission data from data by latching an internal command sequentially by the at least one internal clock in response to the phase control signal and shifting the sequentially latched internal command by a period set by a shifting control signal in response to the delay-locked clock.

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.

Abstract: A system configuration is generated by integrating source models. Transformations are generated according to a weaving model that specifies relations among metamodels of the source models and the system configuration. The transformations, when executed, transform the source models into the system configuration that includes target entities. From the transformations, one or more integration constraints are generated for each target entity to be created or modified by an operation of the transformations. The integration constraints describe semantics of the relations specified by the weaving model. System configuration constraints are formed to include the integration constraints in addition to constraints of each source model. The transformations are executed to transform the source models into the system configuration to generate the system configuration obeying the system configuration constraints.

Abstract: An arithmetic processing device includes: a communication interface configured to transmit a data request corresponding to a data request instruction stored in a data request queue that stores the data request instruction as an entry and to receive data corresponding to the transmitted data request; and a processor configured to perform an operation by using the data received by the communication interface, the processor is configured to cause the communication interface to transition to a power-saving state when the data request queue includes no entry and the processor performs the operation.

Abstract: A computer-implemented method renders user interfaces for devices with multi-image option ROMs according to option ROM dispatch policies associated with the devices. The option ROM dispatch policies can specify whether the multi-image option ROM for the device is enabled or disabled. The option ROM dispatch policies can also specify the image of the multi-image option ROM to execute during boot. The multi-image ROM can include a UEFI compliant image and a legacy BIOS image. The computer-implemented method may receive user selections modifying the option ROM dispatch policies via the rendered user interfaces.

Abstract: Methods and apparatus relating to techniques for shutting down one or more GPU (Graphics Processing Unit) components in response to unchanged scene detection are described. In one embodiment, one or more components of a processor enter a low power consumption state in response to a determination that a scene to be displayed is static. The static scene is displayed on a display device (e.g., based on information to be retrieved from memory) for as long as no change to the static scene is detected. Other embodiments are also disclosed and claimed.

Abstract: In some examples, a peak power system includes a plurality of system components, one or more of the system components to dynamically provide a peak power requirement of the component. The system also includes a peak power manager to receive the peak power requirement of the one or more of the system components. The peak power manager can also dynamically provide, based on a system peak power limit and based on at least one updated peak power requirement received from at least one of the one or more system components, an updated component peak power limit to one or more of the system components.

Abstract: In one embodiment, an apparatus includes: at least one processing circuit; at least one array associated with the at least one processing circuit; a power controller to manage power consumption of the apparatus; and a fabric bridge coupled to the power controller. The fabric bridge and power controller may be configured to implement a handshaking protocol to enable the fabric bridge to receive data from the at least one array via a sideband communication path and send the data to a system memory coupled to the apparatus via a primary communication path, prior to entry of the apparatus into a first low power state. Other embodiments are described and claimed.

Abstract: Embodiments of the present invention relate to a solution for supplying power to a processor. In some embodiments, there is provided a method for supplying power to a processor. The method comprises, in response to determining that an output voltage of a main power supply supplying power to a processor is lower than a predefined threshold, enabling an additional power supply to supply power to the processor. The method further comprises determining output power of the additional power supply. In addition, the method further comprises, in response to determining that the output power of the additional power supply exceeds peak power limit of the additional power supply, sending, by the additional power supply, a signal to the processor to lower a clock frequency of the processor.

Abstract: Systems and methods are disclosed for derivation of executable tasks for synchronizing configuration parameters. An example method may comprise: obtaining a first set of configuration parameters of a first computer system corresponding to a first time value; obtaining a second set of configuration parameters of the first computer system corresponding to a second time value; performing a comparison between the first set of configuration parameters and the second set of configuration parameters to determine one or more differences; deriving in view of the comparison, one or more executable tasks to convert the first set of configuration parameters to the second set of configuration parameters; and providing, to a second computer system, the one or more executable tasks for execution by the second computer system to synchronize configuration parameters of the second computer system to configuration parameters of the first computer system corresponding to the second time value.

Abstract: Methods that can manage power for memory subsystems are provided. One method includes providing power to a set of memory devices via a set of power modules, determining a first amount of power being consumed by the set of memory devices, and in response to a predetermined event, modifying a second amount of power provided to the set of memory devices via a set of spare power modules. Systems and apparatuses that can include, perform, and/or implement the method are also provided.

Abstract: A data processing system includes multiple powered domains which communicate using a bridge 10. The bridge 10 includes first bridge circuitry 14 within a first power domain and second bridge circuitry 16 within a second power domain. The first bridge circuitry 14 and the second bridge circuitry 16 exchange intra-bridge power control signals which serve to control management of the communication channel through the bridge 10 to adopt a communication open state or a communication quiesced state independent of whether either side of the bridge is in a power-active state or a power-inactive state.

Abstract: A method and apparatus for node power regulation among nodes that share a power supply are described. In one embodiment, the apparatus comprises a power supply unit to provide input power and a plurality of nodes coupled to receive the input power, where each node of the plurality of nodes is operable to run power management logic, and wherein two or more nodes of the plurality of nodes alternate between performing power management and providing power regulation control information to other nodes of the plurality of nodes to regulate power consumption by the plurality of nodes, with, at any one time, only one node of plurality of nodes generating the power regulation control to regulate power for the plurality of nodes.

Abstract: The disclosed technology is generally directed to integrated circuit technology with defense-in-depth. In one example of the technology, an integrated circuit includes a set of independent execution environments including at least two independent execution environments. At least two of the independent execution environments are general purpose cores with differing capabilities. The independent execution environments in the set of independent execution environments are configured to have a defense-in-depth hierarchy.

Abstract: An information handling system includes a storage device and a processor. The storage device includes a boot image for the information handling system. The processor determines an architectural location for a boot device for the information handling system, determines that the storage device is located at the architectural location of the information handling system, determines a unique identifier for the storage device, determines from a basic input/output system (BIOS) of the information handling system a BIOS identifier associated with the unique identifier, and places the BIOS identifier at the top of a BIOS boot order list.

Abstract: Systems, methods, and apparatus for internal on-chip clock calibration for devices coupled to a serial bus are described. A data line of the bus is monitored at a device in order to detect select command signals on the data line, where the select command signals have an accompanying clock signal, such as a burst clock, on a clock line of the serial bus sent concurrently with the command signal. The internal on-chip clock generator in the receiving device utilizes the clock signal occurring with the command signal for calibration, where the select signals are those signals sufficiently long enough for a receiving device to effectively utilize the concurrent clock signal for calibration purposes. In this manner, clock calibration for an internal clock is maintained accurately without the need for an extra clock calibration input.