Patents Examined by Xuxing Chen
  • Patent number: 11099619
    Abstract: A chip includes a first pin coupled to a signal line and a controller to detect a state of the signal line using the first pin. The controller controls output of first power to the signal line through the first pin based on a first state of the signal line and prevents output of the first power to the signal line through the first pin based on a second state of the signal line. The signal line may be coupled to provide second power from a power source to a data storage device.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 24, 2021
    Assignee: NXP B.V.
    Inventors: Fabien Boitard, Ludovic Oddoart
  • Patent number: 11086279
    Abstract: An order may be received for an apparatus such as a power converter or other power device, where the apparatus may be housed in a packing box. A configuration device may be programmed with information responsive to details of the order and an ID associated with the apparatus. A label or other identifying object may be created or configured (e.g., printed) and attached to the apparatus or may otherwise accompany the apparatus prior to dispatch of the packing box. The label may provide details of operating parameters of the apparatus responsive to the details of the order. Upon receipt and unpacking of the packing box, the configuration device may be connected to the apparatus, thereby to causing the apparatus to become configured.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: August 10, 2021
    Assignee: Solaredge Technologies Ltd.
    Inventors: Lior Handelsman, Yaron Binder, Yoav Galin, Amir Fishelov, Guy Sella
  • Patent number: 11073882
    Abstract: In an example, a display device with power inputs includes a first power input to receive a first amount of input power, a second power input to receive a second amount of input power, a power allocator to combine at least a portion of the first amount of power with at least a portion of the second amount of power to form a combined output power, and a universal serial bus (USB) port to output at least a portion of the combined output power to a peripheral device.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: July 27, 2021
    Inventors: Humberto M. Fossati, Wen Shih Chen, John W. Frederick
  • Patent number: 11068019
    Abstract: A calibration method for calibrating a clock of a circuit for a smart card, which includes operations for: at a first instant, storing (S310) first time data from a terminal in the clock; at a second instant, reading (S320) second time data from the clock and corresponding to the first time data incremented by the clock as a function of a first duration between the first instant and the second instant; comparing (S330) the second time data with third time data corresponding to the first time data incremented, by the terminal or by a remote server, as a function of the first duration between the first instant and the second instant; as a function of the result of the comparison, calculating (S340) first calibration data; and storing (S350) the first calibration data in the clock. The reading of the second time data may be in a contactless manner.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 20, 2021
    Assignee: IDEMIA FRANCE
    Inventors: Lucien Amiot, Bastien Duong
  • Patent number: 11061458
    Abstract: A first power train that includes a first plurality of components, and a second power train includes a second plurality of components. The first power train is configured to provide power to a first plurality of server racks of a first data center at a first level of high-availability service associated with a first uptime. The first plurality of components includes a first subset of the first plurality of components and a second subset of the first plurality of components. The second power train is configured to provide power to a second plurality of server racks of the first data center at a second level of high-availability service that is associated with a second uptime that is less than the first uptime. The second plurality of components includes a first subset of the second plurality of components and the second subset of the first plurality of components.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: July 13, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Keith A. Krueger, Lalu Vannankandy Kunnath, Kristofer Andrew Johnson, Mark Joseph Baracani, Scott Thomas Seaton, Osvaldo Patricio Morales, Steven Solomon, David Thomas Gauthier
  • Patent number: 11048605
    Abstract: Methods and apparatus relating to techniques for power management. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to generate a voltage/frequency curve for at least one of a core or a sub-core in a processor and manage an operating voltage level of the at least one of a core or a sub-core using the voltage/frequency curve. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 29, 2021
    Assignee: INTEL CORPORATION
    Inventors: Nikos Kaburlasos, Balaji Vembu, Josh B. Mastronarde, Altug Koker, Eric C. Samson, Abhishek R. Appu, Kiran C. Veernapu, Joydeep Ray, Vasanth Ranganathan, Sanjeev S. Jahagirdar
  • Patent number: 11029971
    Abstract: Systems, apparatuses and methods may provide for technology that identifies a first set of compute nodes and a second set of compute nodes, wherein the first set of compute nodes execute more slowly than the second set of compute nodes. The technology may also automatically determine a compute node configuration that results in a relatively low difference in completion time between the first set of compute nodes and the second set of compute nodes with respect to a neural network workload. In an example, the technology applies the compute node configuration to an execution of the neural network workload on one or more nodes in the first set of compute nodes and one or more nodes in the second set of compute nodes.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Meenakshi Arunachalam, Kushal Datta, Vikram Saletore, Vishal Verma, Deepthi Karkada, Vamsi Sripathi, Rahul Khanna, Mohan Kumar
  • Patent number: 11016523
    Abstract: A circuit is provided that has three clock sources, a first processing unit connected to the first clock source, a second processing unit connected to the second clock source, and an input unit. The first processing unit has a first logic circuit and a first memory circuit connected to the first logic circuit, wherein a first set of instructions, which is designed to implement a first control program when executed by the first logic circuit, is stored in the first memory circuit, wherein the first clock source specifies a clock timing of the execution of the first set of instructions. The second processing unit has a second logic circuit and a second memory circuit connected to the second logic circuit, wherein a second set of instructions, which is designed to implement a second control program when executed by the second logic circuit, is stored in the second memory circuit.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: May 25, 2021
    Assignee: WAGO Verwaltungsgesellschaft mbH
    Inventor: Markus Weidner
  • Patent number: 11016554
    Abstract: A semiconductor apparatus includes a plurality of chips and a first bypass switch. The chips are coupled in series between a power end and a reference ground end. The first bypass switch is coupled in series between a first end and a second end of a first chip among the chips, wherein the first end is coupled to the power end and the second end is coupled to the reference ground end. The first bypass switch is turned on according to a first control signal when an operational efficiency of the first chip is less than a threshold value and the first chip is determined to be damaged.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 25, 2021
    Assignee: DigWise Technology Corporation, LTD
    Inventors: JingJie Wu, Shih-Hao Chen, Wen-Pin Hsieh, Chih-Wen Yang
  • Patent number: 11009858
    Abstract: Automation and network components of an industrial automation network are discovered and evaluated using a configured tool that can access the components and determine their interconnection and configuration. The equipment on the network may include automation and monitoring devices, such as controllers, drives, switchgear, and so forth, as well as network components such as servers, routers, industrial managed switches, and so forth. The configuration may be graphically mapped for an operator, and known issues or deficiencies in the detected configuration may be used to evaluate potential problems that can be addressed. The access and evaluation can be done during real-time operation of the system without perturbing its normal automation functions.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: May 18, 2021
    Assignee: Rockwell Automation Technologies, Inc.
    Inventor: Joshua E. Newton
  • Patent number: 10996725
    Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: May 4, 2021
    Assignee: NVIDIA Corporation
    Inventors: Sau Yan Keith Li, Thomas E. Dewey, Arthur Chen, Simon Lai, Amit Pabalkar, Santosh Nayak
  • Patent number: 10990146
    Abstract: Described is a voltage regulator with adaptive gain, which comprises: a plurality of power-gate transistors controllable by a digital bus, the plurality of power-gate transistors operable to provide a first power supply to a load, and to receive a second power supply as input; an analog-to-digital converter (ADC) to receive the first power supply and to generate a digital output representative of the first power supply; and a controller to receive the digital output representative of the first power supply and to generate the digital bus for controlling the plurality of power-gate transistors such that a transfer function of the plurality of power-gate transistors is substantially linear over an operating range.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: April 27, 2021
    Assignee: Intel Corporation
    Inventors: Ramnarayanan Muthukaruppan, Pradipta Patra, Gaurav Goel, Uday Bhaskar Kadali
  • Patent number: 10977050
    Abstract: A memory device includes: a non-volatile memory having a first portion and a second portion which are utilized by a current configuration among a first configuration and a second configuration, a primary booting code is stored in one of the first portion and the second portion, and a backup booting code is stored in the other of the first portion and the second portion. In response that a updated booting code replaces the backup booting code, the updated booting code are performed by a prequalify operation, and the first portion and the second portion being temporarily utilized by another configuration, other than the current configuration, among the first configuration and the second configuration. If the updated booting code is operated successfully, after system reset, the first portion and the second portion being utilized by another configuration among the first configuration and the second configuration.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: April 13, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Chih-Liang Chen
  • Patent number: 10969858
    Abstract: In an embodiment, a power control circuit for an execute circuit is configured to monitor power consumption of operations in a pipeline of the execute circuit and potential changes in power consumption if new operations are issued into the pipeline. The power control circuit may be configured to inhibit issuance of a given operation if the change in power consumption is greater than a maximum increase. A decaying average of previous power consumptions may be maintained and compared to the potential increase in power consumption to control the rate of change in power consumption over time.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: April 6, 2021
    Assignee: Apple Inc.
    Inventors: Daniel U. Becker, Aditya Kesiraju, Srikanth Balasubramanian, Venkatram Krishnaswamy, Boris S. Alvarez-Heredia
  • Patent number: 10955904
    Abstract: A method, an apparatus, a storage medium and an electronic device for processing an application of a mobile terminal are provided. The method includes the following acts. It is detected whether the mobile terminal is currently in standby state. All available sensor connection interfaces are traversed in responding to detecting that the mobile terminal is currently in standby state. It is determined whether an application corresponding to each of the available sensor connection interfaces is in accordance with a filtering condition. The application is exited in responding to determining that the application corresponding to each of the available sensor connection interfaces is not in accordance with the filtering condition, and the application is restrained from holding a corresponding sensor connection.
    Type: Grant
    Filed: May 29, 2017
    Date of Patent: March 23, 2021
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Jun Zhang, Bin Wang
  • Patent number: 10956176
    Abstract: Embodiments of the present application disclose a processing method, a device, a storage medium, and a mobile terminal for implementing automatic startup. The method includes: acquiring, by a processing device for implementing automatic startup, at least one of program startup information and startup call information of an application when it is detected that a startup event for the application occurs; sending, by the processing device for implementing automatic startup, the at least one of the program startup information and the startup call information to a server for acquiring a determination strategy for the application serving as a startup control strategy for the application, wherein the determination strategy is obtained by the server through analyzing the at least one of the program startup information and the startup call information; controlling, by the processing device for implementing automatic startup, startup of the application according to the startup control strategy for the application.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 23, 2021
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Zhiyong Lin, Bing Du
  • Patent number: 10949539
    Abstract: A method may include determining if both of two redundant operating system images for executing functionality of a chassis management controller were found during one or more previous boot sessions of the chassis management controller to be unsecure, wherein each operating system image comprises an integrated kernel and initial file root system stored in a respective first partition of a memory of the chassis management controller, verity hashes of a root file system of such operating system image, the verity hashes stored in a respective second partition of the memory, and the root file system of such operating system image stored in a respective third partition of the memory. The method may also include, in response to determining that one of the two redundant operating system images is secure, initiate verification of such operating system image to determine if such operating system image has indicia of tampering.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: March 16, 2021
    Assignee: Dell Products L.P.
    Inventors: Prakash Nara, Wei Liu, Charles E. Rose, Santosh Kumar, Sudhir Vittal Shetty, Marshal F. Savage, Rhushabh Bhandari, Madhav Karri
  • Patent number: 10949215
    Abstract: A method, computer program product, and system identify a low-cost time to re-boot a system. The method includes a processor obtaining a request for a re-boot of a system. The processor obtains identifiers of uncompleted tasks executing in the system. Based on obtaining the identifiers, the processor obtains a task cost of each task of the uncompleted tasks, where a value of the task cost of each task relates to a portion of each task completed by the processor at a given time. The processor determines, based on the task costs associated with the uncompleted tasks, a re-boot cost for re-booting the system at the given time. The processor determined a system cost for not re-booting the system at the given time. The processor compares the re-boot cost to the system cost to determine whether to re-boot the system at the given time in response to the request.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Vinicio Bombacino, Claudio Falcone, Luca Lazzaro, Andrea Tortosa
  • Patent number: 10942664
    Abstract: Devices, systems and methods for reconfigurable and/or updatable lightweight embedded devices or systems are disclosed. Via use of such a device, system, or method, various capabilities for a user are provided, simplified, secured, and/or made more convenient. The system may interact with various other devices or systems, including those that are cloud-based or communicate through the cloud, and may utilize various local sensors, in order to provide one or more of improved access, monitoring, diagnostics, and so forth.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: March 9, 2021
    Assignee: LIFE365, INC.
    Inventors: Eric Vandewater, Kent Dicks
  • Patent number: 10929150
    Abstract: An optical line terminal and a method for upgrading a primary device and a secondary device of the optical line terminal are provided. The secondary device receives a stepwise reset notification sent by the primary device; the secondary device resets a control chip according to the received stepwise reset notification, and sends a request message to the primary device after the control chip is reset, where the request message is used to request the primary device to deliver new configuration data; the secondary device obtains the new configuration data delivered by the primary device; and the secondary device restores data of the control chip by using the new configuration data delivered by the primary device. In the embodiments of the present disclosure, only the control chip of the secondary device needs to be reset and upgraded, and other hardware structures of the secondary device do not need to be reset.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 23, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiaodong Qiu, Liankui Lin