Patents Examined by Xuxing Chen
  • Information processing apparatus and circuit device
    Patent number: 11327522
    Abstract: An information processing apparatus includes a first controller that operates while receiving first power and executes device-independent control; a second controller that operates while receiving second power and controls a device on a basis of a command from the first controller; a clock management unit that operates while receiving continuous power, and limits supply of a first clock signal to the first controller until the first power is supplied and limits supply of a second clock signal to the second controller until the second power is supplied; and a reset cancellation management unit that operates while receiving continuous power, limits supply of a first reset cancellation signal to the first controller until operation using the first clock signal starts and limits supply of a second reset cancellation signal to the second controller until operation using the second clock signal starts.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: May 10, 2022
    Assignee: FUJIFILM Business Innovation Corp.
    Inventors: Masahiro Kobata, Kenji Imamura, Shinho Ikeda, Kazuhiko Abe, Yuji Murata, Takanori Fukuoka
  • Voltage transition control for USB power delivery sources
    Patent number: 11314300
    Abstract: A circuit includes a controller to communicate with a sink device and communicate a plurality of power sources that are available to the sink device. A plurality of switch devices switch power from one of the plurality of power sources to the sink device in response to a control signal from the controller. A policy engine in the controller defines policies for the operation of the controller during different communications phases between the controller and the sink device.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: April 26, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Deric Wayne Waters
  • Serial lane-to-lane skew reduction
    Patent number: 11314277
    Abstract: Examples described herein provide a method for reducing lane-to-lane serial skew in an integrated circuit. In an example using a processor-based system, a maximum clock skew is determined from clock skews of respective lanes of a transmitter of the IC. Each of the clock skews corresponds to a skew of a clock signal of the respective lane relative to a same reference clock signal. A skew match amount is determined for each lane of the lanes of the transmitter. The skew match amount for a respective lane of the lanes is based on the maximum clock skew and the clock skew of the respective lane. Configuration data is generated to configure the transmitter to shift incoming data for each lane of the lanes based on the skew match amount for the respective lane.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: April 26, 2022
    Assignee: XILINX, INC.
    Inventors: Riyas Noorudeen Remla, Gourav Modi, Azarudin Abdulla, Chee Chong Chan
  • System and method for runtime firmware verification, recovery, and repair in an information handling system
    Patent number: 11314866
    Abstract: A management system for an information handling system includes a memory device and a management controller. The memory device includes a primary firmware image and a backup firmware image. The management controller boots the management system. The boot of the management system includes a read of a first block at an offset within the primary firmware image. The management controller further determines that the read of the first block had a first read error, and reboots the management system in response to determining that the read of the first block had the first read error. The reboot of the management system includes a read of a second block at the offset within the backup firmware image.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: April 26, 2022
    Assignee: Dell Products L.P.
    Inventors: Michael E. Brown, Nagendra Varma Totakura, Vasanth Venkataramanappa, Senthil Kumar, V, Prashanth Giri
  • Firmware anti-rollback
    Patent number: 11301566
    Abstract: A platform security processor is booted and reads a set of write-once memory bits to obtain a minimum security patch level (SPL). The security processor then verifies that a table SPL for a firmware security table is greater than or equal to the minimum SPL. The firmware security table includes a plurality of firmware identifiers for firmware code modules, and a plurality of check SPL values each associated with respective one of the firmware identifiers. The security processor verifies SPL values in a plurality of firmware code modules by, for each firmware code module, accessing the module to obtain its firmware SPL value and check if the respective firmware SPL value is equal to or greater than a respective check SPL value in the firmware security table.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: April 12, 2022
    Assignee: ATI Technologies ULC
    Inventors: Kathirkamanathan Nadarajah, Benedict Chien
  • System and method for user equipment-side thermal mitigation
    Patent number: 11301012
    Abstract: A user equipment may receive thermal mitigation guidelines. The user equipment may generate one or more temperature thresholds based on the thermal mitigation guidelines. The one or more temperature thresholds may define a first temperature zone and a second temperature zone. The user equipment may detect a temperature of the user equipment. The user equipment may identify whether the temperature occurs in the first temperature zone or the second temperature zone. The user equipment may select an action to perform based on whether the temperature occurs in the first temperature zone or the second temperature zone. The user equipment may perform the action to maintain or reduce the temperature of the user equipment.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: April 12, 2022
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Lily Zhu, Deepa Jagannatha, Hui Zhao
  • Operating point management in multi-core architectures
    Patent number: 11287871
    Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Efraim Rotem, Oren Lamdan, Alon Naveh
  • Data processing accelerator having a local time unit to generate timestamps
    Patent number: 11281251
    Abstract: According to one embodiment, a DP accelerator includes one or more execution units (EUs) configured to perform data processing operations in response to an instruction received from a host system coupled over a bus. The DP accelerator includes a security unit (SU) configured to establish and maintain a secure channel with the host system to exchange commands and data associated with the data processing operations. The DP accelerator includes a time unit (TU) coupled to the security unit to provide timestamp services to the security unit, where the time unit includes a clock generator to generate clock signals locally without having to derive the clock signals from an external source. The TU includes a timestamp generator coupled to the clock generator to generate a timestamp based on the clock signals, and a power supply to provide power to the clock generator and the timestamp generator.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: March 22, 2022
    Assignees: BAIDU USA LLC, BAIDU.COM TIMES TECHNOLOGY (BEIJING) CO., LTD.
    Inventors: Yong Liu, Yueqiang Cheng, Jian Ouyang, Tao Wei
  • Power supplying system, electronic apparatus, and power supplying method
    Patent number: 11275422
    Abstract: In a power supplying system, a selection unit that selects one of a first power feed unit and a second power feed unit, a first voltage determination unit that compares a voltage of an output of the first power feed unit with a first threshold value, a second voltage determination unit that compares a voltage of an output of the second power feed unit with a second threshold value, and a management unit that sets the first threshold value and the second threshold value are provided.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: March 15, 2022
    Assignee: FUJIFILM Corporation
    Inventor: Takashi Nagatomi
  • Method and device for setting operating system
    Patent number: 11269656
    Abstract: A method of setting operating system parameters of a device includes: identifying, based on execution of an application, at least one workload type for the application; generating a workload-specific policy corresponding to the at least one workload type; and setting the operating system parameters based on the workload-specific policy.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 8, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Karthikeyan Saravanan, Daniel Ansorregui Lobete, James Bantock
  • Method for converting device tree data into ACPI data for edge device operating in a network
    Patent number: 11263019
    Abstract: A method for generating boot tables for a device having access to device information. It is determined whether there exists at least one system boot table stored in a memory. If it is determined that a system boot table does not exist, the device information is retrieved, and the device information is converted to at least one boot table. The converting includes generating a first boot table by populating the first boot table with information of components of the device that have a correspondence to a computer system boot information standard. The generating also includes generating a second boot table for another component of the device that does not have a correspondence to the computer system boot information standard, by creating an entry in the second boot table that is populated with an identifier used to find a compatible component defined in the computer system boot standard.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: March 1, 2022
    Assignee: VMware, Inc.
    Inventors: Andrei Warkentin, Cyprien Laplace, Ye Li, Alexander Fainkichen, Regis Duchesne
  • Techniques for memory access in a reduced power state
    Patent number: 11256318
    Abstract: Various embodiments are generally directed to techniques for memory access by a computer in a reduced power state, such as during video playback or connected standby. Some embodiments are particularly directed to disabling one or more memory channels during a reduced power state by mapping memory usages during the reduced power state to one of a plurality of memory channels. In one embodiment, for example, one or more low-power mode blocks in a set of functional blocks of a computer may be identified. In some such embodiments, the computer may include a processor, a memory, and first and second memory channels to communicatively couple the processor with the second memory. In many embodiments, usage of the one or more low-power mode blocks in the set of functional blocks may be mapped to a first address range associated with the first memory channel.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: February 22, 2022
    Assignee: INTEL CORPORATION
    Inventors: Binata Bhattacharyya, Paul S. Diefenbaugh
  • System and method for power management of field-programmable gate arrays and load balancing of personality bitstreams from a baseboard management controller
    Patent number: 11256314
    Abstract: An information handling system includes a processor, a system baseboard management controller (BMC), and a field-programmable gate array (FPGA) add-in card. The FPGA add-in card includes an FPGA programmed with accelerated function units (AFUs) to perform processing tasks for the processor. The AFUs include AFUs of a common type. A card BMC provides a temperature indication to the system BMC. The system BMC determines that a temperature of the FPGA add-in card exceeds a temperature threshold based upon the temperature indication, selects one of the common AFUs to be disabled, and directs the card BMC to disable the selected AFU. The card BMC disables the first AFU and not the second AFU in response to the direction to disable the first AFU.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: February 22, 2022
    Assignee: Dell Products L.P.
    Inventors: Jeremiah James Bartlett, Pavan Kumar Gavvala, Rama Rao Bisa, Johan Rahardjo
  • Collaborative processor and system performance and power management
    Patent number: 11221857
    Abstract: The present invention relates to a platform power management scheme. In some embodiments, a platform provides a relative performance scale using one or more parameters to be requested by an OSPM system.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: January 11, 2022
    Assignee: Intel Corporation
    Inventors: Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall, Efraim Rotem, Krishnakanth V. Sistla, Eliezer Weissmann
  • Storage system deep idle power mode
    Patent number: 11216058
    Abstract: Systems and methods are disclosed, including, after a first threshold time after entering an idle power mode of a storage system, without receiving a command from a host device over a communication interface, moving host data stored in volatile memory of the storage system to non-volatile memory of the storage system and transitioning a power mode of the storage system from an idle power mode to a deep idle power mode using control circuitry of the storage system, the deep idle power mode having a second power level lower than a first power level of the idle mode and a second exit latency higher than a first latency of the idle mode. The control circuitry can further determine that the storage system is ready to enter a power savings power mode and provide an indication of the determination using a unidirectional power state signal interface separate from the communication interface.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: January 4, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Qing Liang, Jonathan Scott Parry
  • Droop detection using power supply sensitive delay
    Patent number: 11204635
    Abstract: Aspects of the invention include a circuit having a power supply sensitive delay circuit, a variable delay circuit coupled to the power supply sensitive delay circuit, a delay line coupled to the variable delay circuit, and a logic circuit coupled to the delay line.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: December 21, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Sperling, Pawel Owczarczyk, Akil Khamisi Sutton, Erik English
  • Classification prediction of workload thermal behavior
    Patent number: 11199895
    Abstract: In one embodiment, a method receives data regarding processing of a workload by a processor. The data is input into a prediction engine configured to classify the data into a plurality of workload classifications. Each workload classification describes different temporal behavior of the workload. Then, the method outputs a prediction for at least one of the plurality of workload classifications, wherein the prediction is used to control performance of the processor in an upcoming period of time.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Kam-shing Leung, James Hermerding, II, Muhammad Abozaed, Gilad Olswang, Moran Peri, Ido Karavany, William Freelove, Sudheer Nair, Tahi Hollander, Avishai Wagner
  • Circuit and method for improved battery life during suspend mode
    Patent number: 11194384
    Abstract: Circuit and method for reducing use of battery power during suspend mode operation of a computing device. Output impedance circuitry coupled to voltage regulation circuitry produces a feedback voltage and converts an output signal, produced in response to an input voltage and the feedback voltage, to an output voltage. A portion of the impedance of the output impedance circuitry is altered by control circuitry in response to a control signal, thereby causing changes in the feedback voltage, the output signal and the output voltage.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Timothy Nguyen, Anh Khong, Mingi Park
  • Method and apparatus for streaming map data based on data types
    Patent number: 11188350
    Abstract: An approach is provided for streaming map data based on data types. For example, the approach involves receiving a request to initiate a streaming of a mapping database to a client device. The mapping database includes at least one original data block including data records corresponding to tiles. The approach also involves processing the data records to generate data bundle entries for an after-processing bundle block. Each of the data bundle entries corresponds to a subset of the tiles, and the after-processing bundle block includes a bundle file and a bundle index file. The approach further involves selecting one of the data bundle entries based on a tile of interest in the request. The approach further involves generating a mapping data stream based on the selected data bundle entry. The approach further involves initiating the streaming of the content data in response to the request.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: November 30, 2021
    Assignee: HERE Global B.V.
    Inventors: Maxim Blagay, Ivan Lopit
  • Battery controller, electronic device, battery pack, and battery controlling method
    Patent number: 11188135
    Abstract: A battery controller used in an electronic device supplied with electric power from a battery pack including a rechargeable battery includes a battery monitor for monitoring remaining battery charge in the rechargeable battery, and a power supply controller. The battery monitor issues an alarm when the remaining battery charge lowers to a threshold or below, and, after that, shuts down upon receiving a shut-down command from the power supply controller. The power supply controller sends the shut-down command to the battery monitor upon receiving the alarm from the battery monitor and determining that the remaining battery charge is equal to or below the threshold.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: November 30, 2021
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Junya Kamijima