Abstract: A semiconductor device includes a substrate, a channel layer, a barrier layer, a gate, a strained layer and a passivation layer. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The gate is disposed on the barrier layer. The strained layer is disposed on the barrier layer. The passivation layer covers the gate and the strained layer. The material of the passivation layer differs from that of the strained layer.

Abstract: A semiconductor device package includes a carrier, an electronic component, a connection element and an encapsulant. The electronic component is disposed on a surface of the carrier. The connection element is disposed on the surface and adjacent to an edge of the carrier. The encapsulant is disposed on the surface of the carrier. A portion of the connection element is exposed from an upper surface and an edge of the encapsulant.

Abstract: A semiconductor device includes first to fourth semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins are substantially aligned along a first direction. The third and fourth semiconductor fins are substantially aligned along the first direction. The third and fourth semiconductor fins have a conductivity type different from that of the first and second semiconductor fins. The first gate structure extends across the first and third semiconductor fins substantially along a second direction. The second gate structure extends across the second and fourth semiconductor fins substantially along the second direction. The first and fourth semiconductor fins are substantially aligned along a third direction crossing the first and second directions, and the third direction is substantially parallel with a <100> crystallographic direction.

Abstract: A microelectromechanical system (MEMS) sensor package includes a laminate that provides physical support and electrical connection to a MEMS sensor. A resin layer is embedded within an opening of the laminate and a MEMS support layer is embedded within the opening by the resin layer. A MEMS structure of the MEMS sensor is located on the upper surface of the MEMS support layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary method of forming a semiconductor device comprises forming a fin over a substrate, wherein the fin comprises a first semiconductor layer and a second semiconductor layer comprising different semiconductor materials, and the fin includes a channel region and a source/drain region; forming a dummy gate structure over the substrate and the fin; etching a portion of the fin in the source/drain region; selectively removing an edge portion of the second semiconductor layer in the channel region of the fin such that the second semiconductor layer is recessed, and an edge portion of the first semiconductor layer is suspended; performing a reflow process to the first semiconductor layer to form an inner spacer, wherein the inner spacer forms sidewall surfaces of the source/drain region of the fin; and epitaxially growing a sour/drain feature in the source/drain region.

Abstract: A MEMS device includes a membrane portion, a piezoelectric layer made of a piezoelectric single crystal, a first electrode on a first surface of the piezoelectric layer, a second electrode on a second surface of the piezoelectric layer opposite to the first direction, and a first layer covering the first surface of the piezoelectric layer. At least a portion of the piezoelectric layer is included in the membrane portion. Each of the first electrode and the second electrode has a tapered cross-sectional shape with a width which decreases with increasing distance from the piezoelectric layer on a cross section along a plane vertical to the surface in the first direction.

Abstract: A method includes etching a hybrid substrate to form a recess in the hybrid substrate, in which the hybrid substrate includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the first semiconductor layer, in which after the etching, a top surface of the first semiconductor layer is exposed to the recess; forming a spacer on a sidewall of the recess, in which the spacer is slanted at a first angle relative to a top surface of the first semiconductor layer; reshaping the spacer such that the a first sidewall of the reshaped spacer is slanted at a second angle relative to the top surface of the first semiconductor layer, in which the second angle is greater than the first angle; and performing a first epitaxy process to grow an epitaxy semiconductor layer in the recess after reshaping the spacer.

Abstract: A silicon substrate having a first silicon substrate having a first surface with a cavity and a second surface opposite the first surface; a first silicon oxide film having a thickness d1 on the first surface; a second silicon oxide film having a thickness d2 on a bottom of the cavity; and a third silicon oxide film having a thickness d3 on the second surface, where d1?d3 and d1<d2, or d3<d1 and d2<d1.

Abstract: A method includes forming an etch stop layer over a first side of a device wafer. The method also includes forming a polysilicon layer over the etch stop layer. A handle wafer is fusion bonded to the first side of the device wafer. A eutectic bond layer is formed on a second side of the device wafer. A micro-electro-mechanical system (MEMS) features are etched into the second side of the device wafer to expose the etch stop layer. The exposed etch stop layer is removed to expose the polysilicon layer. The exposed polysilicon layer is removed to expose a cavity formed between the handle wafer and the device wafer.

Abstract: A graphene/doped 2D layered material Van der Waals heterojunction superconducting composite structure, a superconducting device and a manufacturing method therefor, which relate to the technical field of superconducting materials. Said structure includes: a (2n+1)-layered structure formed by graphene layers and doped 2D layered materials which are alternately provided. An outer layer of the layered structure is the graphene layer, n is an integer between 1 to 50, a superconducting region is formed by a region in which the graphene perpendicularly overlaps the doped 2D layered material, and the graphene layers and the doped two-dimensional layered materials are self-assembled into one piece by means of a Van der Waals force.

Abstract: An etchant is utilized to remove a semiconductor material. In some embodiments an oxidizer is added to the etchant in order to react with surrounding semiconductor material and form a protective layer. The protective layer is utilized to help prevent damage that could occur from the other components within the etchant.

Abstract: A semiconductor device includes: a fin-type active region extending on a substrate in a first direction that is parallel to an upper surface of the substrate; and a source/drain region in a recess region extending into the fin-type active region, wherein the source/drain region includes: a first source/drain material layer; a second source/drain material layer on the first source/drain material layer; and a first dopant diffusion barrier layer on an interface between the first source/drain material layer and the second source/drain material layer.

Abstract: An MRAM device includes a bottom electrode over a substrate, a magnetic tunnel junction (MTJ) structure on the bottom electrode, and a top electrode on the MTJ structure. The MRAM device also includes spacers on sidewalls of the top electrode and the MTJ structure, and a first dielectric layer surrounding the spacers. The MRAM device further includes a patterned etch stop layer on the first dielectric layer and the spacers. In addition, the MRAM device includes a second dielectric layer on the patterned etch stop layer, and a top electrode via embedded in the second dielectric layer and in contact with the top electrode and the patterned etch stop layer.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

Abstract: In one example, a method comprises forming a first layer on a substrate surface, forming an opening in the first layer, forming a second layer on the first layer and in the opening, and forming a photoresist layer on the second layer, in which the photoresist layer has a first curved surface over a first part of the first layer and over the opening. The method further comprises etching the photoresist layer and a second part of the second layer over the first part of the first layer to form a second curved surface on the second part of the second layer, and forming a mirror element and a support structure in the second layer, including by etching a third part of the second layer and removing the first layer.

Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.

Abstract: A method of manufacturing a semiconductor structure includes following operations. A first substrate is provided. A plate is formed over the first substrate. The plate includes a first tensile member, a second tensile member, a semiconductive member between the first tensile member and the second tensile member, and a plurality of apertures penetrating the first tensile member, the semiconductive member and the second tensile member. A membrane is formed over and separated from the plate. The membrane include a plurality of holes. A plurality of conductive plugs passing through the plate or membrane are formed. A plurality of semiconductive pads are formed over the plurality of conductive plugs. The plate is bonded to a second substrate. The second substrate includes a plurality of bond pads, and the semiconductive pads are in contact with the bond pads.

Abstract: A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.

Abstract: A load control system may include control devices for controlling power provided to an electrical load. The control devices may include a control-source device and a control-target device. The control-target device may control the power provided to the electrical load based on digital messages received from the control-source device. The control devices may include a load control discovery device capable of sending discovery messages configured to discover control devices within a location. The discovered control devices may be organized by signal strength and may be provided to a network device to enable association of the discovered control devices within a location. The discovery messages may be transmitted within an established discovery range. The discovery range may be adjusted to discover different control devices. Different control devices may be identified as the load control discovery device for discovering different control devices.