Abstract: A method for creating snapshots and backups in a virtual computing environment is provided. The method includes writing application output of an application spanning one or more virtual machines as an application consistency group to a writeback cache, wherein the one or more virtual machines are implemented using one or more compute nodes and wherein the writeback cache is implemented in direct attached storage in the one or more compute nodes. The method includes pausing I/O (input/output) operations of the application and marking the pausing, in the writeback cache. The method includes resuming the I/O operations of the application, after the marking and dumping data, according to the marking, from the writeback cache to a data node, as a snapshot.

Abstract: A solid state drive includes a controller with a hardware interface to fewer planes of memory cells than included in the nonvolatile storage. For example, a controller hardware interface can include a 1N plane interface coupled to a nonvolatile storage device with 2N planes of memory cells. For data access transactions between the controller and the nonvolatile storage device, first and second consecutive 1N plane command sequences are interpreted as a single 2N plane command sequence.

Abstract: A system comprising a processor and a memory storing instructions that, when executed, cause the system to identify a plurality of dump units associated with a translation table in a storage device, determine a plurality of snapshot markers associated with the plurality of dump units, calculate a first value of a first snapshot marker from the plurality of snapshot markers in the storage device, identify a second snapshot marker from an additional source, the second snapshot marker having a second value satisfying the first value, retrieve a dump unit associated with the second snapshot marker from the additional source, and reconstruct the translation table using the dump unit.

Abstract: A computer processor that implements pre-translation of virtual addresses is disclosed. The computer processor may include a register file comprising one or more registers. The computer processor may include processing logic. The processing logic may receive a value to store in a register of one or more registers. The processing logic may store the value in the register. The processing logic may designate the received value as a virtual address, the virtual address having a corresponding virtual base page number. The processing logic may translate the virtual base page number to a corresponding real base page number and zero or more real page numbers corresponding to zero or more virtual page numbers adjacent to the virtual base page number. The processing logic may further store in the register of the one or more registers the real base page number and the zero or more real page numbers.

Abstract: Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system is disclosed. In this regard, a compressed memory controller provides multiple CI hint directory entries, each providing a plurality of CI hints. The compressed memory controller receives a memory write request comprising write data, determines a compression pattern for the write data, and generates a CI for the write data based on the compression pattern. The compressed memory controller writes the write data to the memory line, and writes the generated CI into one or more ECC bits of the memory line. In parallel, the compressed memory controller determines whether the physical address corresponds to a CI hint directory entry, and, if so, a CI hint of the CI hint directory entry corresponding to the physical address is updated based on the generated CI.

Abstract: Providing memory bandwidth compression using multiple last-level cache (LLC) lines in a central processing unit (CPU)-based system is disclosed. In some aspects, a compressed memory controller (CMC) provides an LLC comprising multiple LLC lines, each providing a plurality of sub-lines the same size as a system cache line. The contents of the system cache line(s) stored within a single LLC line are compressed and stored in system memory within the memory sub-line region corresponding to the LLC line. A master table stores information indicating how the compressed data for an LLC line is stored in system memory by storing an offset value and a length value for each sub-line within each LLC line. By compressing multiple system cache lines together and storing compressed data in a space normally allocated to multiple uncompressed system lines, the CMC enables compression sizes to be smaller than the memory read/write granularity of the system memory.

Abstract: Described is a system and method for efficient pointer chasing in systems having a single memory node or a network of memory nodes. In particular, a pointer chasing command is sent along with a memory request by an issuing node to a memory node. The pointer chasing command indicates the number of interdependent memory accesses and information needed for the identified interdependent memory accesses. An address computing unit associated with the memory node determines the relevant memory address for an interdependent memory access absent further interaction with the issuing node or without having to return to the issuing node.

Abstract: Efficient processing of user data read requests in a deduplicated data storage system places the metadata for most frequently requested data in data structures and locations in the system hierarchy where the metadata will be most rapidly available. The total amount of such metadata makes storing all of the metadata in high speed memory expensive, and the system and method described uses both the temporal and the spatial characteristics of the user system activity in any epoch to adjust the contents of metadata cache so as to respond to the dynamics of a multi user or multi-application environment where the storage system is not made aware of the time changing mix of operations except by observation of the individual requests. A history record is used to promote metadata from the slow memory to the fast memory, and a process selection may be adjusted based on the address-space activity.

Abstract: A method for adaptive offloading of data movement from a computer system includes identifying performance results from a plurality of SCSI extended copy (XCOPY) operations associated with a storage unit, each XCOPY operation of the plurality of XCOPY operations including one or more parameters. The method also includes selecting, based on the identified performance results, one or more XCOPY parameters for the storage unit from the plurality of XCOPY operations. The method further includes forming an XCOPY operation associated with the storage unit, the XCOPY operation including the one or more selected XCOPY parameters. The method also includes transmitting the XCOPY operation to the storage unit.

Abstract: Example embodiments of the present invention relate to methods, systems, and a computer program product for storing data compressed according to a level of activity of a data set. The method includes evaluating a level of activity for a data set and selecting a compression algorithm according to the level of activity of the data set. The data set then may be compressed according to the selected compression algorithm and the compressed data stored in a data storage system.

Abstract: A nonvolatile memory having memory blocks, and a controller configured to select a first block and a second block among the memory blocks, determine a third percentage on the basis of a first percentage of valid data in the first block and a second percentage of valid data in the second block, determine a first ratio between a write amount of user data in accordance with a request from a host and a write amount of the valid data in the first block on the basis of the third percentage, and write the user data and the valid data in the first block into the nonvolatile memory on the basis of the first ratio.

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

Abstract: Embodiments relating to garbage collection for a deduplicated and compressed storage device are described. One embodiment provides for a data storage system comprising an array of redundant storage devices including a first set of storage devices to be configured as live storage devices and a second set of storage devices to be configured as spare storage devices, a spare storage device to be enabled in event of a failure of a live storage device; and a set of processing devices coupled to the array of redundant storage devices, the set of processing devices to execute logic to enable data replication and deduplication for the array of redundant storage devices and perform distributed deduplication garbage collection on the first set of storage devices using one or more devices in the second set of storage devices as temporary storage.

Abstract: Techniques for performing garbage collection on an object array using array chunk references is described. A garbage collector (GC) thread identifies an object array to be processed. The GC thread divides the object array into array chunks. The GC thread generates array chunk references corresponding respectively to the array chunks. Each array chunk reference comprises: (a) chunk start bits representing a memory address of a start of a corresponding array chunk, and (b) chunk length bits representing a chunk length of the corresponding array chunk. The GC thread pushes the array chunk references onto the processing stack. A single processing stack concurrently stores multiple array chunk references, associated with a same object array. One or more of the array chunk references, that are associated with the same object array and stored on the processing stack, may be distributed to other GC threads for processing.

Abstract: Providing memory bandwidth compression using compression indicator (CI) hint directories in a central processing unit (CPU)-based system is disclosed. In this regard, a compressed memory controller provides a CI hint directory comprising a plurality of CI hint directory entries, each providing a plurality of CI hints. The compressed memory controller is configured to receive a memory read request comprising a physical address of a memory line, and initiate a memory read transaction comprising a requested read length value. The compressed memory controller is further configured to, in parallel with initiating the memory read transaction, determine whether the physical address corresponds to a CI hint directory entry in the CI hint directory. If so, the compressed memory controller reads a CI hint from the CI hint directory entry of the CI hint directory, and modifies the requested read length value of the memory read transaction based on the CI hint.

Abstract: Provided are an apparatus and method for using block windows configured in a memory module to provide block level access to memory chips in the memory module. A plurality of block windows are configured that map to addresses corresponding to the addressable locations in the memory chips. A read/write request is received indicating a requested read or write operation with respect to a target block window comprising one of the block windows. The requested read or write operation is performed with respect to the addresses that map to the target block window.

Abstract: Provided are an apparatus and method for enforcing timing requirements for a memory device. An event command directed to a target addressable location comprising one of the addressable locations is received. A determination is made as to whether a time difference of a current time and a timestamp associated with a completed event directed to a threshold location including the target addressable location exceeds a time threshold. The received event command is executed against the target addressable location in response to determining that the time difference exceeds the time threshold.

Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

Abstract: A system, computer program product, and computer-executable method including presenting, to an application, data storage from a data storage system including a fast tier (FT) of data storage and a capacity tier (CT) of data storage, wherein the data storage system is enabled augment data stored within the data storage system to facilitate moving data between tiers of data storage within the data storage system, analyzing data stored on the FT of the data storage system to determine whether the application is sending write I/Os associated with the data, upon a negative determination, augmenting the data for the CT, and moving the data to the CT.

Abstract: A storage device with a memory may include memory block leveling that improves data retention by considering localized temperature. A block's distance from a heat source may result in variance of data retention. The localized temperature may be used to improve data retention through a relocation, refreshing, or leveling of blocks that considers their physical location on the die and/or in the package.