Abstract: Systems, methods, and/or devices are used to manage high-priority NAND operations. In some embodiments, the method includes receiving a first command (e.g., requesting a high-priority memory operation) corresponding to a first location (e.g., having both a first physical address and a first aliased physical address) in a first die of a plurality of physical non-volatile memory die in a storage device. If the first die is performing a blocking low-priority memory operation (e.g., the low-priority operation was sent to the first die using a second physical address), the method includes sending a memory operation command, corresponding to the first memory operation, to the first die using the first aliased physical address. In some embodiments, a predefined die-selection portion of the second physical address matches the predefined die-selection portion of the first physical address and does not match the predefined die-selection portion of the first aliased physical address.

Abstract: A method of distributing data in a distributed storage system includes receiving a file and dividing the received file into chunks. The chunks are data-chunks and non-data chunks. The method further includes grouping chunks into a group and determining a distribution of the chunks of the group among storage devices of the distributed storage system based on a maintenance hierarchy of the distributed storage system. The maintenance hierarchy includes hierarchical maintenance levels and maintenance domains. Each maintenance domain has an active state or an inactive state; and each storage device is associated with at least one maintenance domain. The method also includes distributing the chunks of the group to the storage devices based on the determined distribution. The chunks of the group are distributed across multiple maintenance domains to maintain an ability to reconstruct chunks of the group when a maintenance domain is in the inactive state.

Abstract: The invention relates to retrieving data from a storage system. One embodiment of the invention comprises receiving a write operation, establishing a correspondence relationship between a logic block address and a physical block address of the write operation, and determining whether a valid data percentage in a mapping table is greater than a predetermined threshold after the correspondence relationship is added in stored metadata of stored metadata.

Abstract: A computer system for copying a source file to a destination file using a virtual memory manager of a computer operating system is provided. One or more processors, one or more non-tangible computer-readable storage devices, and a plurality of program instructions are included. The program instructions provide for receiving, by the virtual memory manager, a request to copy the source file to a destination file. The program instructions further provides that based on the status of the virtual page, performing at least one moving the virtual page to the destination file, copying the virtual page to the destination file, reading the virtual page into memory, and ignoring the virtual page.

Abstract: An electronic device with volatile memory repeatedly compares an amount of free volatile memory to a first predetermined threshold level of free volatile memory. When the device determines that the amount of free volatile memory is less than the first predetermined threshold level, the device deallocates volatile memory by terminating one or more processes based on predetermined priority levels of the one or more processes.

Abstract: Optimizing copy operations in a storage array, including: receiving a plurality of copy operations; detecting a triggering event that causes a storage array controller to initiate execution of the plurality of copy operations; and combining, in dependence upon a metadata optimization policy, the plurality of copy operations into a single copy operation.

Abstract: A computer program product for copying a source file to a destination file using a virtual memory manager of a computer operating system is provided. The computer program product includes receiving, by the virtual memory manager, a request to copy the source file to a destination file. The computer program product further provides that based on the status of the virtual page, performing at least one moving the virtual page to the destination file, copying the virtual page to the destination file, reading the virtual page into memory, and ignoring the virtual page.

Abstract: A memory device for multiple processors capable of processing a plurality of memory access requests and a memory system having the same are provided. The memory device includes one command and control signal port configured to receive a command and control signal from a memory controller, one address port configured to receive an address signal from the memory controller, a data port configured to form a plurality of data channels being independently driven to simultaneously process a plurality of memory access requests of the memory controller, and a plurality of memory banks divided into a plurality of sub-banks to simultaneously perform operations according to the plurality of memory access requests when the plurality of memory access requests are sequentially transmitted through the command and control signal port and the address port.

Abstract: A compute server accomplishes physical address to virtual address translation to optimize physical storage capacity via thin provisioning techniques. The thin provisioning techniques can minimize disk seeks during command functions by utilizing a translation table and free list stored to both one or more physical storage devices as well as to a cache. The cached translation table and free list can be updated directly in response to disk write procedures. A read-only copy of the cached translation table and free list can be created and stored to physical storage device for use in building the cached translation table and free list upon a boot of the compute server. The copy may also be used to repair the cached translation table in the event of a power failure or other event affecting the cache.

Abstract: In one embodiment, a method includes determining a size of a file associated with each job in a job queue of files to be migrated to one of a plurality of drives that includes at least one of each of the following: a faster drive and a relatively slower drive. The availability of a faster drive is determined. The file associated with the job in the job queue having a file size larger than a threshold is sent to the faster drive.

Abstract: Systems and methods for multicast tree-based data distribution in a distributed shared cache. An example processing system comprises: a plurality of processing cores, each processing core communicatively coupled to a cache; a tag directory associated with caches of the plurality of processing cores; a shared cache associated with the tag directory; a processing logic configured, responsive to receiving an invalidate request with respect to a certain cache entry, to: allocate, within the shared cache, a shared cache entry corresponding to the certain cache entry; transmit, to at least one of: a tag directory or a processing core that last accessed the certain entry, an update read request with respect to the certain cache entry; and responsive to receiving an update of the certain cache entry, broadcast the update to at least one of: one or more tag directories or one or more processing cores identified by a tag corresponding to the certain cache entry.

Abstract: A mass storage memory system and method of operation are disclosed. The memory system includes an interface adapted to receive data from a host system, a plurality of memory die and a controller, where the controller is configured to read or write data synchronously across a plurality of die connected to different channels based on a first command, and to read or write data asynchronously and independently in different die in the same channel based on a second command. The controller may program data in a maximum unit of programming for a single memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die.

Abstract: A transactional execution of a set of instructions in a transaction of a program may be initiated to collect memory operand access characteristics of a set of instructions of a transaction during the transactional execution. The memory operand access characteristics may be stored upon a termination of the transactional execution of the set of instructions. The memory operand access characteristics may include an address of an accessed storage location, a count of a number of times the storage location is accessed, a purpose value indicating whether the storage location is accessed for a fetch, store, or update operation, a count of a number of times the storage location is accessed for one or more of a fetch, store, or update operation; a translation mode in which the storage location is accessed; and an addressing mode.

Abstract: Systems and methods disclosed herein are used to efficiently configure a plurality of memory caches. In one aspect, a method includes a server receiving or accessing a storage policy including a first caching mode for a first set of one or more virtual machine elements and a second caching mode for a second set of one or more virtual machine elements. If a virtual machine element requires configuration, the server determines whether the virtual machine element is a virtual machine element of the first set or the second set. If the virtual machine element is a virtual machine element of the first set, the server applies the first caching mode to a section of a logical solid state drive. If the virtual machine element is a virtual machine element of the second set, the server applies the second caching mode to the section of the logical solid state drive.

Abstract: Transactional execution of a transaction beginning instruction initiates prefetching, by a CPU, of discontiguous storage locations specified by a list. The list includes entries specifying addresses and may also include corresponding metadata. The list may be specified by levels of indirection. Fetching of corresponding discontiguous cache lines is initiated while in TX mode. Additional instructions in the transaction may be executed and use the prefetched cache lines.

Abstract: A circuit for controlling the operation of a memory system having different types of memory is described. The circuit comprises a first memory having a first type of memory element and having a first access time; a second memory having a second type of memory element and having a second access time, wherein the second type of memory element is different than the first type of memory element; a memory control circuit enabling access to the first memory and the second memory; a delay buffer coupled to the second memory to compensate for a difference in the first access time and the second access time; and a circuit for merging outputs of the first memory and delayed outputs of the second memory to generate ordered output data. A method of controlling the operation of a memory system is also disclosed.

Abstract: Embodiments are described for methods and systems for mapping virtual memory pages to physical memory pages by analyzing a sequence of memory-bound accesses to the virtual memory pages, determining a degree of contiguity between the accessed virtual memory pages, and mapping sets of the accessed virtual memory pages to respective single physical memory pages. Embodiments are also described for a method for increasing locality of memory accesses to DRAM in virtual memory systems by analyzing a pattern of virtual memory accesses to identify contiguity of accessed virtual memory pages, predicting contiguity of the accessed virtual memory pages based on the pattern, and mapping the identified and predicted contiguous virtual memory pages to respective single physical memory pages.

Abstract: A device or system includes a plurality of storage resources each associated with a respective performance class, each being associated with selected performance characteristics such as IOPS, bandwidth, etc. The device or system includes a compute instance having access to allocated storage resources, the allocated storage devices including one or more storage resources. The device or system also includes an optimization component adapted to obtain information relating to utilization by the compute instance component of the allocated storage resources, determine that a change to the allocated storage resources is necessary, based on the information, cause data to be migrated from a first storage resource associated with a first performance class to a second storage resource associated with a second storage class, and cause a removal from the allocated storage resources of the first storage resource and an addition to the allocated storage resources of the second storage resource.

Abstract: Example embodiments of the present invention relate to a method, an apparatus, and a computer program product for updating disk geometry in a multipathing environment. The method includes receiving a disk geometry update for a logical unit on a storage array accessible via a multipathing device in the multipathing environment. The method then includes translating the disk geometry update for the logical unit for each respective disk device aggregated by the multipathing device. Requests for the logical unit then may be issued according to the updated geometry.

Abstract: A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command.