Abstract: Efficient processing of user data read requests in a deduplicated data storage system places the metadata for most frequently requested data in data structures and locations in the system hierarchy where the metadata will be most rapidly available. The total amount of such metadata makes storing all of the metadata in high speed memory expensive, and the system and method described uses both the temporal and the spatial characteristics of the user system activity in any epoch to adjust the contents of metadata cache so as to respond to the dynamics of a multi user or multi-application environment where the storage system is not made aware of the time changing mix of operations except by observation of the individual requests. A history record is used to promote metadata from the slow memory to the fast memory, and a process selection may be adjusted based on the address-space activity.

Abstract: A method for maintaining a storage mapping table. An access interface is directed to read a group mapping table from the last page of a block of a storage unit. The block is allocated to store data of a plurality of groups, each group stores information indicating which location in the storage unit stores data of an LBA (Logical Block Address) range, and the group mapping table stores information indicating which unit of the block stores the latest data of each group. The group mapping table is stored in a DRAM (Dynamic Random Access Memory). The access interface is directed to read data of each group from the storage unit according to the group mapping table. The data of each group is stored in a specified location of a storage mapping table of the DRAM.

Abstract: Technologies for region-based cache management includes network computing device. The network computing device is configured to divide an allocated portion main memory of the network computing device into a plurality of memory regions, each memory region having a cache block that includes a plurality of cache lines of a cache memory of the processor. The network computing device is further configured to determine whether a cache line selected for eviction from the cache memory corresponds to one of the plurality of memory regions and, if so, retrieve a dynamically adjustable bias value (i.e., a fractional probability) associated with the corresponding memory region. Additionally, the network computing device is configured to generate a bias comparator value for the corresponding memory region, compare the bias value of the corresponding memory region and the bias comparator value generated for the corresponding memory region, and determine whether to evict the cache line based on the comparison.

Abstract: A Green NAND Device (GND) driver application queries AC line and battery status and then stores an image of processor states and caches and a resume routine to DRAM when power failure occurs. A DRAM image is then stored to flash memory for a persistent mode when battery power is available. The image in DRAM may be a partial image that includes entries, flushed caches, processor contexts, ramdisks, write caches, and a resume context. Endurance of flash memory is increased by a Super Enhanced Endurance Device (SEED) SSD. In a power down mode, the GND driver limits DRAM use and only caches in DRAM data that can be deleted on power down. Host accesses to flash are intercepted by the GND driver and categorized by data type. Paging files and temporary files cached in DRAM are optionally written to flash.

Abstract: A data processing system (DPS) uses platform protection technology (PPT) to protect some or all of the code and data belonging to certain software modules. The PPT may include a virtual machine monitor (VMM) to enable an untrusted application and a trusted application to run on top of a single operating system (OS), while preventing the untrusted application from accessing memory used by the trusted application. The VMM may use a first extended page table (EPT) to translate a guest physical address (GPA) into a first host physical address (HPA) for the untrusted application. The VMM may use a second EPT to translate the GPA into a second HPA for the trusted application. The first and second EPTs may map the same GPA to different HPAs. Other embodiments are described and claimed.

Abstract: A technique for operating a Hyper-Converged Infrastructure (HCI) system includes running an IO stack on a physical computing server of the HCI system. The IO stack exposes multiple protocol endpoints for providing host applications with access to data objects. Protocol endpoints are exposed both to host applications running within the HCI system and to host applications running on external computing devices, thus enabling the HCI system to double as a data storage system with respect to external computing devices.

Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

Abstract: Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and controller circuitry may include a user logic interface, a memory controller, and a physical layer input-output interface. The user logic interface may be operated in a first clock domain. The memory controller may be operated in a second clock domain. The physical layer interface may be operated in a third clock domain that is an integer multiple of the second clock domain. The user logic interface may include only user-dependent blocks. The physical layer interface may include memory protocol agnostic blocks and/or memory protocol specific blocks. The memory controller may include both memory protocol agnostic blocks and memory protocol dependent blocks. The memory controller may include one or more color pipelines for scheduling memory requests in a parallel arbitration scheme.

Abstract: Described are techniques for partitioning processors in a system. At a first point in time, a short term workload ratio and a long term workload ratio are determined. At the first point in time, the system is in a first workload state having a first configuration including a first portion of the processors performing front end processing tasks and a second portion of the processors performing back end processing tasks. A first value is determined where the first value is an absolute value of a difference between the short term workload ratio and the long term workload ratio. First processing is performed that determines, in accordance with the first value and the short term workload ratio, whether to adjust any of the first portion of the processors and the second portion of the processors of the first configuration.

Abstract: An operating method of a storage device which includes a nonvolatile memory is provided. The operating method includes performing a first program operation on selected memory cells of the nonvolatile memory and storing a first time when the first program operation is performed; and adjusting a program parameter according to a difference between the first time and a second time, and performing a second program operation on the selected memory cells using the adjusted program parameter, the second time being a time when the second program operation is performed.

Abstract: A method for scheduling read commands, performed by a processing unit, including at least the following steps. Logical read commands are received from a master device via a first access interface, where each logical read command requests to read data of a logical address. First physical storage locations of mapping segments associated with the logical addresses are obtained from a high-level mapping table, and a second access interface is directed to read the mapping segments from the first physical storage locations of a storage unit. Second physical storage locations associated with the logical addresses are obtained from the mapping segments, and the second access interface is directed to read data from the second physical storage locations of the storage unit. The first access interface is directed to clock the data of the logical addresses out to the master device.

Abstract: A computationally implemented system and method that is designed to, but is not limited to: obtain information at least in part regarding one or more first aspects of one or more intermediate electronic communication devices for serving as one or more nodes of one or more standby point-to-point communication networks upon activation thereof for use by an origination electronic communication device to communicate at least in part with a destination electronic communication device, the one or more intermediate electronic communication devices having one or more second aspects as one or more mobile electronic communication devices. In addition to the foregoing, other method aspects are described in the claims, drawings, and text forming a part of the present disclosure.

Abstract: A method for controlling hierarchical storage including: a first step for storing first information relating to the association between the specific processes and the storage regions of the storage tiers; a second step for obtaining second information relating to the access operations of the specific processes as a function of time; a third step for obtaining third information relating to the amount of access to the storage regions as a function of time; and a fourth step for identifying the time of occurrence of a change in the amount of access, from the second information and the third information on the basis of the first information, and determining, according to the identified time of occurrence of the change in the amount of access, a transfer initiation time at which data in the storage regions is to be transferred between storage tiers.

Abstract: A method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the following steps. A write command for programming at least a data page into a first address is received from a master device via an access interface. It is determined whether a block of data to be programmed has been collected, where the block contains a specified number of pages. The data page is stored in a DRAM (Dynamic Random Access Memory) and cache information is updated to indicate that the data page has not been programmed into the storage unit, and to also indicate the location of the DRAM caching the data page when the block of data to be programmed has not been collected.

Abstract: Described are techniques for processing a write operation that writes first data to a target location of a logical address range of a logical device. It is determined whether the target location is mapped to physical storage. Responsive to determining that the target location is not mapped to physical storage, performing first processing to service the write operation. The first processing includes sending the write operation along with a hint to a caching layer where the hint indicates to store zeroes to locations that do not include user data. The caching layer forms a data portion denoting data stored at a logical address subrange of the logical device. The logical address subrange includes the target location. The data portion includes the first data and zeroes stored at remaining locations of the logical address subrange not including user data. The data portion is stored in cache by the caching layer.

Abstract: As disclosed herein a method, executed by a computer, for enabling live partition mobility using ordered memory migration includes receiving a request to initialize a migration of a logical partition (LPAR) to a destination system. The method further includes creating a list which includes memory page identifiers corresponding to memory pages of the LPAR. The memory page identifiers of the list are ordered according to a page transfer priority. The method further includes identifying memory pages of the LPAR that will be unmodified during an estimated duration of time of the migration. The method further includes updating the list, based on the identified memory pages of the LPAR that will be unmodified during the estimated duration of time of the migration. The method further includes migrating the LPAR based on the list. A computer system, and a computer program product corresponding to the method are also disclosed herein.

Abstract: An information processing apparatus includes a first memory, and a processor coupled to the first memory and configured to: specify a number of virtual machines executed on each node of a plurality of nodes on an information processing system that performs as a plurality of virtual machines, and calculate a value indicating a degree of deviation of the number of the virtual machines between the plurality of nodes.

Abstract: In an embodiment, a processor includes at least one core to execute instructions and a memory controller coupled to the at least one core. In turn, the memory controller includes a spare logic to cause a dynamic transfer of data stored on a first memory device coupled to the processor to a second memory device coupled to the processor, responsive to a temperature of the first memory device exceeding a thermal threshold. Other embodiments are described and claimed.

Abstract: In a transactional memory environment, a computer-implemented method includes receiving one or more memory locations and broadcasting, by a first processor to one or more additional processors, a cross-interrogate. The cross-interrogate includes the one or more memory locations. The computer-implemented method further includes, by the one or more additional processors, receiving the cross-interrogate, not aborting any current transaction based on the cross-interrogate, and generating an indication. The indication comprises whether the one or more memory locations is in use for the current transaction by that of the one or more additional processors. The computer-implemented method further includes sending the indication from each of the one or more additional processors to the first processor and, by the first processor, combining each indication from the one or more additional processors to yield a status code and returning the status code.

Abstract: In one embodiment, a computer-implemented method includes encountering a store operation during a compile-time of a program, where the store operation is applicable to a memory line. It is determined, by a computer processor, that no cache coherence action is necessary for the store operation. A store-without-coherence-action instruction is generated for the store operation, responsive to determining that no cache coherence action is necessary. The store-without-coherence-action instruction specifies that the store operation is to be performed without a cache coherence action, and cache coherence is maintained upon execution of the store-without-coherence-action instruction.