Abstract: The present technology relates to a memory controller and a method of operating the same. The memory controller may include a block manager designating a first memory block as an open block, which is driven to program m-bit data per cell, where m is a natural number, an address manager increasing an access count value corresponding to a logical address for the first memory block whenever a program request or a read request including the logical address is received from a host, and a data manager determining a representative attribute of data programmed in the first memory block based on access count values for the logical addresses for the first memory block when a flush request is received from the host. The block manager may determine whether to designate a new open block according to the determined representative attribute.

Abstract: The present disclosure generally relates to increasing data storage device lifetime by detecting synthetic PLP tests. Both upper and lower PLP time thresholds are set. When the PLP time is above the upper threshold, the data storage device is in a defensive PLP idle state. When the PLP time is between the upper and lower thresholds, the data storage device is in a defensive PLP detecting state. When the PLP time is below the lower threshold, the data storage device may enter the defensive PLP state if the number of times the PLP time is below the lower PLP time threshold either a consecutive number of times or a set number of times within a predefined window of time. While in the defensive PLP state, mounting is not completed and hence, a host device will not send any I/O commands and thus, not waste a PEC count.

Abstract: An information processing apparatus that functions as a SUB controller that, for a command group formed of pairs each formed by a command prepared by a host controller and a status, executes processing of each command and returns a status of an execution result of the command processing. In response to a request for processing the command group from the host controller, the SUB controller acquires the command group therefrom as an original command sequence. The original command sequence is divided into a plurality of segments each formed by one or more commands and having a total volume not larger than a threshold. Command groups each formed of pairs each formed by a command and a status are independently set in one or more storage devices connected to the information processing apparatus. Each storage device is notified of a command processing request on a segment-by-segment basis.

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

Abstract: This application discloses a data writing method, device, a storage server and a computer readable storage medium, including: writing, when a write request is received, write data corresponding to the write request to a write buffer; acquiring historical access data of a data block corresponding to to-be-flushed data in the write buffer when a data flushing operation is triggered for the write buffer; determining whether the to-be-flushed data is write-only data based on the historical access data by using a pre-trained classifier; if yes, writing the to-be-flushed data to a hard disk drive; and if no, writing the to-be-flushed data to a cache. The data writing method provided by this application can effectively reduce the traffic of writing dirty data to the cache while reserving more space in the cache for the ordinary data, thereby improving the utilization of the cache space and the read hit rate of the cache.

Abstract: A storage system is described. The storage system may include a plurality of storage tiers, each including at least one storage device, each storage device including storage and a controller. Metadata storage may store metadata for an image stored in the plurality of storage tiers, which includes a location in the plurality of storage tiers where the image is stored. A receiver may receive a request to access the image from a host. Retrieval software, executed by a processor, may retrieve the image from the plurality of storage tiers using the location where the image is stored. A transmitter may transmit the image to the host.

Abstract: A data management system comprises: an outsourcer terminal outsourcing a fabrication by an instruction document; an outsourcee terminal receiving outsourcing and/or sub-outsourcing; and a server device. The server device comprises: a data management unit managing a proprietary authority of data stored in a data storage unit; an order container storage unit storing an order container with which data stored in the data storage unit is correlated, for each order created in an order creation unit of the outsourcer terminal and/or the outsourcee terminal; and an order container management unit managing sharing of the order container, based on an instruction from an order container sharing authority management unit of the outsourcer terminal and/or the outsourcee terminal. The server device, for each order, correlates any format of data element stored with the order container, for management.

Abstract: An information processing apparatus according to an embodiment includes: a creation processing unit which creates information indicating a message structure based on which a length of a memory area to be secured in a stack area of a virtual address space assigned for a serialization process is determined during compilation; a serialization processing unit which performs a serialization process to serialize data from a device and write the serialized data into a data storage device using the information created by the creation processing unit; and a deserialization processing unit which reads the serialized data written into the data storage device and deserializes the read data using the information created by the creation processing unit.

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

Abstract: A method for storing data, the method comprising receiving, by an offload component in a client application node, an augmented write request originating from an application executing in an application container on the client application node, wherein the augmented write request is associated with data and wherein the offload component is located in a hardware layer of the client application node, and processing, by the offload component, the augmented write request by a file system (FS) client and a memory hypervisor module executing in a modified client FS container on the offload component, wherein processing the request results in at least a portion of the data being written to a location in a storage pool.

Abstract: Methods, systems, and devices for performing memory command verification are described. A system may include a memory device and a memory controller, which may be external (e.g., a host device). The memory device may receive, from the memory controller, a command indicating a type of operation and an address. The memory device may decode the command and execute an operation (e.g., the operation corresponding to the decoded command) at an execution location on the memory device. The system (e.g., the memory device or the memory controller) may determine whether the executed operation and execution location match the type of operation and address indicated in the command, and the system may thereby determine an error associated with the decoding, the execution, or both of the command.

Abstract: A method for providing a piece of data in a communication system. The method includes: allocating a memory means for updating data in the memory means, in particular by a producer, in particular in response to a request signal of the producer; updating the data in the provided memory means with the piece of data; providing the memory means for the purpose of being read out, in particular by a consumer, wherein, in the allocation step, the memory means is allocated as a function of a status of the memory means.

Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.

Abstract: A memory device includes a memory, a secure-access circuit, a plain-access circuit, and protection hardware. The memory includes at least a secure-storage partition assigned a first address range and a plain-storage partition assigned a second address range, disjoint from the first address range. The secure-access circuit is configured to access the secure-storage partition by generating addresses in the first address range. The plain-access circuit is configured to access the plain-storage partition by generating addresses in the second address range. The protection hardware is configured to prevent the plain-access circuit from accessing the first address range assigned to the secure-storage partition.

Abstract: A storage device projected temperature environment configuration system includes storage devices with the same physical hardware configuration, and a computing device manufacturing system that manufactures computing devices.

Abstract: A multi-memory apparatus that uses machine learning is described. The apparatus may include an interface controller, a non-volatile memory, and a volatile memory. The interface controller may cause the apparatus to receive a first command from a host device. The interface controller may cause the apparatus to communicate the first command to a machine learning engine and to circuitry configured to store and manage commands for the non-volatile memory and the volatile memory. The interface controller may further cause the apparatus to communicate a second command generated by the machine learning engine to the circuitry. The second command may be based on information determined by the machine learning engine during a training mode.

Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.

Abstract: A system may include a memory and a processor in communication with the memory configured to perform operations. The may operations include obtaining transaction logs in blocks from nodes of a data storage system. The operations may include, for each transaction log, splitting the transaction log into log entries, grouping log entries into groups associated with a same data source, and writing the log entries of the groups to empty blocks such that log entries from different groups do not share a same block. The operations may include identifying a same sequence of log entries from the written transaction logs and uploading first blocks of a first transaction log, including the same sequence of log entries, to an object-based storage without uploading second blocks of a second transaction log including the same sequence of log entries to the object-based storage.

Abstract: A method includes receiving, at a direct memory access (DMA) controller of a memory device, a first command from a first cache controller coupled to the memory device to prefetch first data from the memory device and sending the prefetched first data, in response to receiving the first command, to a second cache controller coupled to the memory device. The method can further include receiving a second command from a second cache controller coupled to the memory device to prefetch second data from the memory device, and sending the prefetched second data, in response to receiving the second command, to a third cache controller coupled to the memory device.

Abstract: Methods, systems, and devices for speed bins to support memory compatibility are described. A host device may read a value of a register including serial presence detect data of a memory module. The serial presence detect data may be indicative of a timing constraint for operating the memory module at a first clock rate, where the timing constraint and the first clock rate may be associated with a first speed bin. The host device may select, for communication with the memory module, a second speed bin associated with a second clock rate at the host device and the timing constraint, where the host device may support operations according to a set of timing constraints that includes a set of values. The timing constraint may be selected from a subset of the set of timing constraints, where the subset may be exclusive of at least one of the set of values.