Abstract: Portions of configuration state registers in-memory. An instruction is obtained, and a determination is made that the instruction accesses a configuration state register. A portion of the configuration state register is in-memory and another portion of the configuration state register is in-processor. Processing associated with the configuration state register is performed. The performing processing is based on a type of access and whether the portion or the other portion is being accessed.

Abstract: An information handling system may include at least one processor; and a non-transitory memory coupled to the at least one processor. The information handling system may be configured to: receive health information for a plurality of node information handling systems; determine, based on the received health information, a score for each of the plurality of node information handling systems; determine an upgrade ordering for the plurality of node information handling systems based on the respective scores for the plurality of node information handling systems; and cause the node information handling systems to perform an upgrade procedure according to the upgrade ordering.

Abstract: According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.

Abstract: Methods, systems, and apparatuses related to computational storage are described. For example, storage accessible to an accelerator may be shared between and, accessible to either of, a host and the accelerator. A computational storage system may include storage providing a portion of a shared file system accessible by a host and by accelerator logic of the computational storage system. Host interface logic may be configured to receive a storage command from the host to store data on the storage at a time the data is created. The host interface logic may be further configured to receive a storage command from the host for the accelerator logic to perform a computational task using the stored data on the storage. The accelerator logic can perform the computational task using the stored data on the storage.

Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.

Abstract: In a case of exchanging a migration source storage controller and a migration destination storage controller sharing one storage medium during replacement of storage devices, when hardware configurations or data management forms of the storage controllers are different, data in the storage medium cannot be shared even when data management information can be copied. Accordingly, a storage system, having a storage control unit and a storage drive provided with a storage medium, includes data management information for accessing data in the storage drive. A first storage control unit copies data management information about the data in the storage drive to a second storage control unit. When a write request is received from a host after copying of the data management information begins, each of the first storage and second storage control units stores write data related to the write request in a separate storage area of the storage drive.

Abstract: Apparatuses, systems, and methods corresponding to hierarchical memory systems are described. Logic circuitry can be resident on a persistent memory device, thereby reducing latencies associated with transferring data between the logic circuitry and the persistent memory device. Logic circuitry on a persistent memory device may include an address register configured to store logical addresses corresponding to stored data. The logic circuitry may receive a redirected request (e.g., prior to redirection, directed to a non-persistent memory device) to retrieve a portion of the data stored in the persistent memory device, determine, in response to receipt of the request to retrieve the portion of the stored data, a physical address corresponding to the portion of the data based on the logical address stored in the address register, and cause the data to be retrieved from the persistent memory device.

Abstract: A controller for controlling a nonvolatile memory device comprising: a read count table including a plurality of read count data, wherein each of the read count data includes a read count value for one data storage region; a read count address table including a read count address indicating an address of a memory region where the read count data is stored; a flash translation layer (FTL) configured to control an operation of the nonvolatile memory device, and manage the read count table and the read count address table; and a flash interface layer (FIL) configured to control data communication between the FTL and the nonvolatile memory device, and update the read count value based on the read count address when read operation is performed on the data storage region.

Abstract: Methods, systems, and devices for multi-level receivers with various operating modes (e.g., on-die termination mode, termination-off mode, etc.) are described. Different modes may be utilized for receiving different types of signaling over a channel. Each mode may correspond to the use of a respective set of receivers configured for the different types of signaling. For example, a device may include a first set of receivers used to receive a first type of signal (e.g., with the channel being actively terminated) and a second set of receivers used to receive a second type of signal (e.g., with the channel being non-terminated). When communicating with another device, based on the type of signaling used for communications, either the first set of receivers or the second set of receivers may be enabled (e.g., through selecting a receiver path for the corresponding mode).

Abstract: Provided are an apparatus and method for a statistical memory network. The apparatus includes a stochastic memory, an uncertainty estimator configured to estimate uncertainty information of external input signals from the input signals and provide the uncertainty information of the input signals, a writing controller configured to generate parameters for writing in the stochastic memory using the external input signals and the uncertainty information and generate additional statistics by converting statistics of the external input signals, a writing probability calculator configured to calculate a probability of a writing position of the stochastic memory using the parameters for writing, and a statistic updater configured to update stochastic values composed of an average and a variance of signals in the stochastic memory using the probability of a writing position, the parameters for writing, and the additional statistics.

Abstract: A memory device to manage the assignment of offset voltages for read operations, and to adjust read voltages using the offset voltages. The offset voltages are dynamically adjusted by a controller during operation of the memory device in response to read errors. In one approach, a first bin of offset voltages is assigned to a first region of a storage media. The first offset voltages are used to adjust read voltages for reading a page of first memory cells in the first region. The controller determines that at least one error has occurred in reading the page. In response to determining the error, the controller determines second offset voltages that can be used to read the first memory cell without causing a read error. Based on the second offset voltages, the controller identifies third offset voltages for assigning to the first region. The third offset voltages are used for adjusting read voltages for subsequent reads of pages in the first region.

Abstract: A method, computer program product, and computing system for allocating a portion of a storage system for storing input/output (IO) traces, thus defining an IO trace storage tier. The plurality of IO traces may be stored within the IO trace storage tier. It may be determined whether at least a threshold number of IO traces are stored within the IO trace storage tier. In response to determining that at least the threshold number of IO traces are stored within the IO trace storage tier, at least a portion of the plurality of IO traces may be offloaded to a client computing device.

Abstract: One or more programming operations are performed to program initial host data at the memory sub-system. The initial host data is received from a host system. A set of usage parameter values associated with the initial host data programmed at the memory sub-system is determined in view of the one or more programming operations. A media management operation is scheduled to be performed between a first time period and a second time period. The first time period corresponds to a time period during which the memory sub-system is expected to receive a first set of subsequent host data. The second time period corresponds to another time period during which the memory sub-system is expected to receive a second set of subsequent host data.

Abstract: A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.

Abstract: One example method includes defining a configuration of SCM, receiving a stream of IOs from a client, analyzing the stream of IOs and, based on the analyzing, estimating future IO behavior of the client, and based on estimated future IO behavior of the client, reconfiguring one or more parameters of the configuration of the SCM to define an updated configuration of the SCM, and the updated configuration of the SCM enables an improvement in IO performance relative to an IO performance of the configuration of the SCM.

Abstract: Methods, systems and devices for configuring access to a memory device are disclosed. The configuration of the memory device may be carried out by creating a plurality of access profiles that are adapted to optimize access to the memory device in accordance with a type of access. For example, when an application with specific memory access needs is initiated, the memory access profile that is designed for that particular access need may be utilized to configure access to the memory device. The configuration may apply to a portion of the memory device, a partition of the memory device, a single access location on the memory device, or any combination thereof.

Abstract: Techniques for accessing a storage system involve: based on a detection that a first host configured to use a first protocol to access a storage system is connected to the storage system, determining a source logical storage space from a second group of logical storage spaces associated with a second protocol. The second protocol is different from the first protocol. The techniques further involve: determining, from a first group of logical storage spaces associated with the first protocol, a target logical storage space to which the source logical storage space is mapped. The techniques further involve: allocating the target logical storage space to the first host, so that the first host accesses the storage system via the target logical storage space. Accordingly, suitable protocols can be flexibly used to access the storage system without cumbersome and time-consuming operations.

Abstract: A technique includes, in response to a cache miss occurring with a given processing node of a plurality of processing nodes, using a directory-based coherence system for the plurality of processing nodes to regulate snooping of an address that is associated with the cache miss. Using the directory-based coherence system to regulate whether the address is included in a snooping domain is based at least in part on a number of cache misses associated with the address.

Abstract: A method includes using a memory address map, locating a first portion of an application in a first memory and loading a second portion of the application from a second memory. The method includes executing in place from the first memory the first portion of the application, during a first period, and by completion of the loading of the second portion of the application from the second memory. The method further includes executing the second portion of the application during a second period, wherein the first period precedes the second period.

Abstract: A data processing system (DPS) uses platform protection technology (PPT) to protect some or all of the code and data belonging to certain software modules. The PPT may include a virtual machine monitor (VMM) to enable an untrusted application and a trusted application to run on top of a single operating system (OS), while preventing the untrusted application from accessing memory used by the trusted application. The VMM may use a first extended page table (EPT) to translate a guest physical address (GPA) into a first host physical address (HPA) for the untrusted application. The VMM may use a second EPT to translate the GPA into a second HPA for the trusted application. The first and second EPTs may map the same GPA to different HPAs. Other embodiments are described and claimed.