Abstract: A stacked memory device includes memory dies over a base die. The base die includes separate memory channels to the different dies and external channels that allow an external processor access to the memory channels. The base die allows the external processor to access multiple memory channels using more than one external channel. The base die also allows the external processor to communicate through the memory device via the external channels, bypassing the memory channels internal to the device. This bypass functionality allows the external processor to connect to additional stacked memory devices.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method for operating the same. An operation of writing metadata in multiple memory dies in the memory device is started, and an erase operation is then performed, when the request for the erase operation exists, with regard to some of the multiple memory dies. Accordingly, the time taken to write metadata can be uniformly adjusted to the largest extent, and the magnitude of peak power consumed by the memory device can be minimized.

Abstract: Systems, methods and apparatus of optimizing neural network computations of predictive maintenance of vehicles. For example, a data storage device of a vehicle includes: a host interface configured to receive a sensor data stream from at least one sensor configured on the vehicle; at least one storage media component having a non-volatile memory; and a controller. The non-volatile memory is configured into multiple partitions (e.g., namespaces) having different sets of memory operation settings configured for different types of data related to an artificial neural network (ANN). The partitions include an output partition configured to store output data from the ANN. The sensor data stream is applied in the ANN to predict a maintenance service of the vehicle. The memory units of the input partition can be configured for cyclic sequential overwrite of selected outputs that are updated less frequently than inputs to the ANN.

Abstract: A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.

Abstract: An agent module of a host directs I/O requests accessing a first disk of a first storage array to access a second disk of a second storage array. The agent module obtains a disk identifier of a first disk in the first storage array and a disk identifier of a second disk in the second storage array to record a mapping relationship between them. The agent module further reports virtual path information for a virtual path between the agent module and a multipath module of the host to the multipath module. The agent module sends the disk identifier of the first disk via the virtual path after receiving a disk identifier query request for querying the identifier of the second disk. Thus, the agent module can send an I/O request for accessing the first disk to the second storage array to access the second disk.

Abstract: A memory system including a non-volatile memory device storing data; and a controller configured to receive a request for an input/output operation regarding the data from a host processor to perform the input/output operation. After receiving a delegated task which is distinguished from the input/output operation, the controller is further configured to perform the delegated task independently and store a result of the delegated task in the non-volatile memory device.

Abstract: A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.

Abstract: Providing persistent storage to transient cloud computing services, including: creating a cloud computing instance, wherein the cloud computing instance is created on on-premises cloud infrastructure; and storing, in non-volatile storage in a storage system that is communicatively coupled to the on-premises cloud infrastructure, data associated with the cloud computing instance.

Abstract: Systems and methods provide improved bus efficiency in read operations by a solid-state device (SSD) installed in an Information Handling System. A read operation is received that requests data stored in a die of the SSD. A command is issued to the die for use of a first read voltage in retrieving the requested data. Upon receiving confirmation that the die has retrieved the requested data, a command is issued to the die to configure a second read voltage for use in retrieving data requested by a second read operation received by the SSD. Concurrent with the die setting the second read voltage for use in retrieving the data requested in the second read operation, a command is issued to initiating transfer, by the die, of the data retrieved for the first read operation. In this manner, idle intervals in the bus used to service the die are eliminated.

Abstract: A method extracts human-interpretable entity profiles from a text-labeled data graph of a system having a plurality of entities. The data graph includes nodes representing the entities and edges between the nodes representing links between the entities. A plurality of text is respectively associated with the corresponding edges. The method includes: constructing neural network layers configured such that each of the edges between a pair of the nodes is modeled as a function of the associated text and cluster representations of the pair of the nodes; for each one of the pair of nodes, performing machine learning to learn a tensor to capture patterns among the associated text and the pair of nodes, and extracting the entity profiles from the tensor.

Abstract: An electronic device includes a memory, an input-output memory management unit (IOMMU), a processor that executes a software entity, and a page migration engine. The software entity and the page migration engine perform operations for preparing to migrate a page of memory that is accessible by the at least one IO device in the memory, the software entity and the page migration engine set migration state information in a page table entry for the page of memory based on the operations being performed. When the operations for preparing to migrate the page of memory are completed, the page migration engine migrates the page of memory in the memory. The IOMMU uses the migration state information in the page table entry to control one or more operations of the IOMMU.

Abstract: The present disclosure relates to an electronic device. A memory controller controlling a memory package including a plurality of memory dies each including a plurality of memory blocks, the plurality of memory blocks controlled in units of super blocks each including at least one memory block selected from each of the plurality of memory dies includes a reclaim information storage storing reclaim information including read counts and migration level information related to the read counts, and a read reclaim controller migrating data stored in a target block having a read count exceeding a threshold count, and victim blocks selected according to the reclaim information to another super block different from a super block to which the target block belongs, wherein the victim blocks include memory blocks whose migration level information is the highest among memory blocks included in memory dies different from a memory die including the target block.

Abstract: A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising: a control signal register storing a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising an initial source address, an initial destination address, a first source stride length in a first dimension, and a first source stride count in the first dimension; a source address register communicatively coupled to the control signal register; a destination address register communicatively coupled to the control signal register; a first source stride counter communicatively coupled to the control signal register; and control logic communicatively coupled to the control signal register, the source address register, and the first source stride counter.

Abstract: Techniques are described for offloading remote direct memory operations (RDMOs) to “execution candidates”. The execution candidates may be any hardware capable of performing the offloaded operation. Thus, the execution candidates may be network interface controllers, specialized co-processors, FPGAs, etc. The execution candidates may be on a machine that is remote from the processor that is offloading the operation, or may be on the same machine as the processor that is offloading the operation. Details for certain specific RDMOs, which are particularly useful in online transaction processing (OLTP) and hybrid transactional/analytical (HTAP) workloads, are provided.

Abstract: Disclosed are various embodiments for improving resiliency and performance of clustered memory. A computing device can acquire a chunk of byte-addressable memory from a cluster memory host. The computing device can then identify an active set of allocated memory pages and an inactive set of allocated memory pages for a process executing on the computing device. Next, the computing device can store the active set of allocated memory pages for the process in the memory of the computing device. Finally, the computing device can store the inactive set of allocated memory pages for the process in the chunk of byte-addressable memory of the cluster memory host.

Abstract: A common storage management device for a system including a common storage and at least one computer includes at least one processor, the at least one computer storing a plurality of applications configured to write and read data in the common storage. The at least one processor is configured to manage a reservation and a release of a storage space of the common storage in response to a request from the plurality of applications. The at least one processor is configured to assign a releasing priority to each storage space of the common storage that is reserved. The at least one processor is configured to instruct to release the storage space with highest releasing priority when the plurality of applications request to reserve the storage space for the data and free storage space is insufficient for reserving the storage space for the data.

Abstract: An apparatus comprises a plurality of memory cells; a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and a controller to transpose a value indicative of a voltage of the first cell to the sense node; isolate the sense node from the bitline; and calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter.

Abstract: Aspects of the present disclosure relate to improving response rates of input/output (IO) requests targeting undefined virtual storage devices. In embodiments, an (IO request can be received by a storage array. Additionally, a determination of whether the IO request targets an undefined target track can be made. Further, source data related to the IO request can be located. For instance, a direct image lookup (DIL) can be performed to locate the source data. Also, a storage-related operation on the undefined target track can be performed using instructions provided by the IO request, such as updating a version of the undefined track. Further, a storage resource allocation for the undefined target track can be destaged.

Abstract: A control apparatus that is connected to a host controller, a first storage unit, and a second storage unit, and that is configured to perform mirror control of the first storage unit and the second storage unit, allocates in order readout requests accepted from the host controller as a readout request corresponding to the first storage unit or a readout request corresponding to the second storage unit, reads out data from the first storage unit and the second storage unit based on at least one allocated readout request, and transmits the readout data to the host controller.

Abstract: Disclosed are various embodiments for improving the resiliency and performance for clustered memory. A computing device can mark a page of the memory as being reclaimed. The computing device can then set the page of the memory as read-only. Next, the computing device can submit a write request for the contents of the page to individual ones of a plurality of memory hosts. Subsequently, the computing device can receive individual confirmations of a successful write of the page from the individual ones of the plurality of memory hosts. Then, the computing device can mark the page as free in response to receipt of the individual confirmations of the successful write from the individual ones of the plurality of memory hosts.