Abstract: A system and method that measures the code non-linearity of a phase mixer (PMIX) during active operation of a clock and data recovery (CDR) circuitry. The PMIX circuitry generates a clock signal based on the PMIX codes. The PMIX circuitry receives a plurality of codes and based on the code value, adjusts the phase of the PMIX output clock signal. A number of times each of the plurality of PMIX codes occurs within a respective time period is determined. Non-linearity values are determined based on the number of times. The non-linearity values are stored in a memory.

Abstract: A signal transceiver apparatus includes: a first communication module and a second communication module; a first switch connected to a first terminal of the first communication module and a first terminal of the second communication module, respectively; a second switch connected to a first transmitting/receiving port and a first signal reception port of the first communication module, and a first antenna structure connected to the second switch; and a third switch connected to a second transmitting/receiving port and a second signal reception port of the second communication module, and a second antenna structure connected to the third switch. The first communication module corresponds to a first transmitting link and two receiving links, and the second communication module corresponds to a second transmitting link and two receiving links.

Abstract: A communication circuit is disclosed. The communication circuit includes a calibration system, configured to receive clock signals respectively having first and second clock phases, and first and second duty cycles, where the calibration system is further configured to receive input data and to adjust the input data to generate adjusted data based partly on the input data and based partly on the first and second duty cycles. The communication circuit also includes a mixer, configured to receive the clock signals and to receive the adjusted data, where the mixer is configured to generate output data based on the clock signals and the adjusted data, and where a mismatch in the output data caused by the first and second duty cycles being different is reduced because of the adjustment made to the input data to generate the adjusted data.

Abstract: A data slicer may include an input transistor configured to generate an internal output voltage based on an input voltage at an input node. An output node may be configured to output an output voltage based on the internal output voltage, and a feedback transistor may be configured to adjust the internal output voltage based on a correction voltage corresponding to output of the output node in a previous cycle.

Abstract: The present disclosure proposes an adaptive non-speculative DFE with an extended time constraint for a PAM-4 receiver and a method for operating the same. An adaptive non-speculative DFE with an extended time constraint for a PAM-4 receiver according to the present disclosure comprises a Continuous-Time Linear Equalizer (CTLE) to boost high-frequency components of an input signal, a Track and Hold (T&H) circuit to track and hold an output of the CTLE, and a sampler, wherein the sampler includes a Decision Feedback Equalization (DFE) sampler to equalize an output of the T&H circuit and sample an output of the T&H circuit in a DFE sampling clock phase; and a DATA sampler to sample a signal equalized by the DFE sampler in a DATA sampling clock phase, wherein the DFE sampling clock phase differs from the DATA sampling clock phase.

Abstract: Methods and apparatus for receiving a user message in a communication network are disclosed. In an exemplary embodiment, a method includes receiving data samples in an uplink transmission from user equipment, performing preamble detection on the data samples, generating a trigger signal that indicates when a preamble is detected, and decoding a user message in response to the trigger signal, wherein the user message follows the detected preamble.

Abstract: A frequency-locked loop (FLL) logic circuit, including a validity signal generator configured to receive an external clock signal and determine whether a glitch occurs in the external clock signal; a clock divider configured to generate a reference frequency clock signal based on the external clock signal and a determination result of the validity signal generator; a synchronizer configured to synchronize a phase of an oscillator clock signal with a phase of the reference frequency clock signal; a clock counter configured to count a number of pulses of the oscillator clock signal during a reference time; and a code limiter configured to determine a range of a frequency selection value for calibrating an operating frequency of the oscillator clock signal based on the counted number of pulses.

Abstract: A data formatting module of a low voltage drive circuit (LVDC) includes a sample and hold circuit, an interpreter, a first buffer, a digital to digital converter circuit, and a data packeting circuit. The sample and hold circuit is operable to sample and hold an n-bit digital value of filtered digital data to produce an n-bit sampled digital data value. The interpreter is operable to convert the n-bit sampled digital data value into interpreted n-bit sampled digital data. The interpreter is operable to write the interpreted n-bit sampled digital data into the first buffer in accordance with a write clock until a digital word is formed. The digital to digital converter circuit is operable to format the digital word to produce a formatted digital word. The data packeting circuit is operable to generate a data packet from the formatted digital word and output the data packet as received digital data.

Abstract: A transmitter for generating a radio frequency, RF, transmit signal is provided. The transmitter includes signal generation circuitry configured to generate, based on a sequence of first control words each indicating a respective frequency shift with respect to a target frequency of the RF transmit signal, a RF carrier signal with sequentially varying frequency over time in order to frequency spread the RF transmit signal. Further, the transmitter includes modulation circuitry configured to generate the RF transmit signal by modulating the RF carrier signal with a modulation control signal. The transmitter additionally includes modification circuitry configured to generate the modulation control signal by modifying, based on the sequence of first control words, phase information of a baseband signal bearing information to be transmitted or phase information of a signal derived from the baseband signal in order to frequency de-spread the RF transmit signal.

Abstract: A method and device for realizing beam alignment are disclosed. The method may include: when first signals are received by two analog subarrays having a same polarization using receiving beams with a same beam direction, acquiring the first signals and the phase center difference therebetween; maintaining the beam direction, changing the phase center difference between the two analog sub-arrays for the first time, and acquiring second signals and the first changed phase center difference; maintaining the beam direction, changing the phase center difference for the second time, and acquiring third signals and the second changed phase center difference; and estimating a DOA of a received signal according to the obtained information, and directing the centers of the receiving beams to the estimated DOA.

Abstract: Communicating using spread spectrum. A legacy RF signal is intercepted from a legacy radio. Spread spectrum processing is performed on the legacy RF signal to create a spread signal. The spread signal is transmitted to a receiver, whereafter the spread signal is de-spread to recover the legacy RF signal.

Abstract: A transmission method simultaneously transmitting a first modulated signal and a second modulated signal at a common frequency performs precoding on both signals using a fixed precoding matrix and regularly changes the phase of at least one of the signals, thereby improving received data signal quality for a reception device.

Abstract: A decision feedback equalizer includes a summer, a slicer, and a feedback circuit. The summer is configured to receive an input signal and a correction signal from the feedback circuit and generate a summer output signal. The slicer includes a first slicer and a second slicer, both are configured to receive the summer output signal as an input, and output a slicer output signal. The feedback circuit is configured to receive the slicer output signal, and based on the slicer output signal, generate the correction signal. The input signal is received at a first clock rate. The first slicer and the second slicer sample the input signal at a second clock rate, about half the first clock rate.

Abstract: Receivers, methods, and cores, can provide decision feedback equalization with efficient burst error correction. An illustrative receiver includes: a decision feedback equalizer that derives symbol decisions from a receive signal; a subtractor that determines an equalization error for each said symbol decision; and a post-processor that operates on the symbol decisions and equalization error to detect and correct symbol decision errors. An illustrative receiving method includes: using a decision feedback equalizer to derive symbol decisions from a filtered receive signal; determining an equalization error for each said symbol decision; and processing the symbol decisions and equalization error to detect and correct symbol decision errors. An illustrative semiconductor intellectual property core generates circuitry for implementing a receiving and method as described above.

Abstract: A method for transmitting covertly employs three features in a novel combination to create a transmission waveform that has no detectable artifacts. First, the method employs spread spectrum, such as a direct sequence spread spectrum signal, to transmit the power level below the noise floor. Second, the method modulates the phase of each chip in the spread spectrum signal using a chaotic sequence. Third, the method filters the transmission signal using a pulse shaped filter to depress blind detection features in the amplitude modulation and higher order power spectral densities. The novel combination of these features results in a practically invisible and undetectable transmission waveform. Many other features are disclosed herein to optimize this combination.

Abstract: A communication device, including a plurality of transceiver modules; a storage configured to store calibration information; and at least one processor configured to: generate a first dual-polarized RF signal by controlling a first transceiver module to generate a first RF signal based on the calibration information; measure, by a second transceiver module, a first signal power of the first dual-polarized RF signal; adjust a parameter of the first transceiver module, and generate a second dual-polarized RF signal by controlling the first transceiver module to generate a second RF signal based on the adjusted parameter; measure, by the second transceiver module, a second signal power of the second dual-polarized RF signal; and generate an aligned dual-polarized RF signal by controlling the plurality of transceiver modules to generate a plurality of RF signals based on a result of a comparison between the first signal power and the second signal power.

Abstract: Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. In embodiment, a single-ended receiver trains DFE coefficients and the slicer reference voltage to improve the received eye height. The process for training avoids many whole range sweeps thereby shortening training time. A custom data pattern that includes low-frequency (DC with respect to DFE) and high-frequency (AC with respect to DFE) worst cases is used for training in a closed loop manner. Negative DFE is used to measure the AC height of the data. Positive DFE is used to find the DC height of the data pattern.

Abstract: A signal transmitter is provided. The signal transmitter includes a signal splitting module, including M output interfaces, where the signal splitting module is configured to split a signal into N sub-signals, and output the N sub-signals through N of the M output interfaces, where M and N are integers, M?2, N?1, and M?N, an integrated array traveling-wave tube amplifier, including M radio frequency channels, where the M channels one-to-one correspond to the M output interfaces, each channel is configured to perform power amplification on a sub-signal that is output from a corresponding output interface, and each channel is openable and closeable, a power supply module, configured to supply power to the integrated array traveling-wave tube amplifier, and at least one transmit antenna, configured to send a signal obtained through power amplification.

Abstract: Proposed are an ultra-low jitter low-power phase-locked loop using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) and an operating method thereof. The proposed PG-ILFM PD includes a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal SREF and a fundamental sampling phase detector (FSPD) configured to receive an output signal SILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO).

Abstract: A receiver device according to an embodiment includes a equalizer, a sampler, and a controller. The equalizer receive a first signal. The equalizer boosts the first signal to output a resultant as a second signal. The sampler samples the second signal. The sampler outputs a sampling result of the second signal as a first digital signal. The controller executes adaptive processing for adapting an amount of boost of the first signal. In the adaptive processing, the controller is configured to: adjust an amount of boost for the equalizer based on inter-symbol interference of a part in the first digital signal, the part matching a data pattern of a set pattern filter; and dynamically change a pattern filter to be set according to the amount of boost for the equalizer.