Abstract: A method of realization of adaptive equalization and an adaptive equalizer. The adaptive equalizer comprises an equalizer unit, which is used for equaling an input signal according to a compensation coefficient to obtain an output signal; a sampling comparison unit, which is connected to an output of the equalizer and is used for sampling a comparison result of the output signal of the equalizer and a reference voltage corresponding to reference voltage step; a data processing unit, which is connected to the sampling comparison unit and the equalizer unit. It is used for scanning a reference voltage step to determine range of the reference voltage steps to which step the amplitude of the output signal is corresponding; and scanning a compensation coefficient step, and determining the compensation coefficient for equalization according to the range of reference voltage steps.

Abstract: Various embodiments relate to an adaptive linear driver, including: a continuous time linear equalizer (CTLE); a programmable transmit driver coupled with an output of the CTLE, wherein the transmit driver includes a first control port configured to receive a first control signal configured to adjust the output level of the programmable transmit driver; an output comparator coupled to an output of the programmable transmit driver, wherein the output comparator is configured to compare the output of the programmable transmit driver with a reference signal and to produce a first comparison signal; and a controller coupled to the output comparator and the first control port, wherein the controller produces a first control signal based upon the first comparison signal.

Abstract: Multiphase switched mode power supply clock apparatus, systems, articles of manufacture, and related methods are disclosed. An example apparatus includes a first clock recovery circuit to in response to obtaining a first clock pulse, transmit the first clock pulse to a power converter to cause the power converter to switch based on the first clock pulse, in response to obtaining a second clock pulse after the first clock pulse re-transmit the second clock pulse to a second clock recovery circuit, and increment a count value, and in response to the count value meeting a phase selection value, reset the count value.

Abstract: A PAM-4 DFE receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). An immediate value of the MSB is used to select a set of ISI offsets used to resolve the LSB. Resolved values of the prior values of the MSB and LSB are then used to select the ISI offset for the immediate symbol.

Abstract: A decision feedback equalizer (DFE) sampler circuit is disclosed. The DFE sampler includes a front-end circuit configured to generate a filtered signal using a plurality of signals that encode a serial data stream that includes a plurality of data symbols and a summing circuit configured to generate an equalized signal by combining the filtered signal and an analog feedback signal based on a digital feedback signal. The DFE sampler further includes first and second samplers configured to sample the equalized signal and generate first and second regeneration signals, respectively, during first and second time periods. A compensation circuit is configured to generate the digital feedback signal using the first and second regeneration signals. The first and second samplers, in alternating time periods, cancel ISI from the equalized signal using the first and second regeneration signals, respectively.

Abstract: A method of equalizing a communication link includes setting a number of coefficients to a required number, determining a number of pulse responses for a waveform, setting all values in a set of values to zero, repeating, until all values have been assigned, determining a current lowest parameter, using a position of the current lowest parameter as an index, determining a minimum value between a first term multiplied by a main pulse response minus a summation of each parameter multiplied by each value, divided by the current lowest parameter, and a corresponding pulse response, and assigning the minimum value to the value having a position equal to the position of the current lowest parameter, and determining a value of each coefficient in a set of coefficients by multiplying each value with the sign of a corresponding pulse response; defining an equalizer having a number of taps having a value based on the corresponding coefficient; and applying the equalizer to a waveform.

Abstract: Radio transceiver control interfaces are provided herein. In certain embodiments, a semiconductor die includes a group of transmitters and a group of receivers that operate as a transceiver. Additionally, a group of common pins are used to control settings of both the transmitters and receivers. In one example, data received on the common pins can be used to establish enable settings for each of the transmitters and receivers. Thus, rather than using a one-to-one correspondence between a pin and the setting of a particular transmitter or receiver, a mapping is used between the common pins and the settings of the transmitters and receivers.

Abstract: To compensate for intersymbol interference, a serial data receiver circuit included in a computer system may include an equalizer circuit that includes a digital-to-analog converter circuit. Based on previously received symbols, the equalizer circuit modifies a signal received via a communication channel or link prior to clock and data recovery. In cases when the digital-to-analog converter circuit becomes saturated, the equalizer circuit additionally uses a dither signal to modify the received signal.

Abstract: A receiver includes a plurality of linear equalizers receiving an input signal; and a plurality of samplers configured to sample a plurality of equalization signals output from the plurality of linear equalizers according to a clock signal. Each of the plurality of linear equalizers compares the input signal with a reference voltage among a plurality of reference voltages to determine a level of the input signal.

Abstract: An apparatus includes a radio frequency (RF) receiver to receive packets. The RF receiver includes first and second synchronization field detectors (SFDs). The first and second SFDs detect synchronization headers generated using first and second physical layer (PHY) modes, respectively.

Abstract: A radio frequency (RF) switch system, an RF switch protective circuit, and a protecting method thereof are provided. The RF switch system may include an RF switch and a protective circuit. The RF switch may be connected between a port that receives an RF signal and a ground. The protective circuit may detect a first voltage that is a voltage that is generated when the first RF switch is turned off, and may transmit an impedance value that is varied based on the first voltage to the port.

Abstract: Disclosed are some examples of Phase interpolator circuitry used in retimer systems. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track a plurality data packets. Phase interpolator circuitry is coupled with clock data recovery circuitry. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal.

Abstract: Aspects presented herein may enable a UE to determine whether phase continuity is to be maintained for one or more uplink transmissions when the UE is configured with a frequency-hopping with zero frequency offset. In one aspect, a UE receives, from a network entity, an indication of frequency hopping with zero frequency offset. The UE determines whether phase continuity is to be applied to UL transmissions based on the indication of the frequency hopping with zero frequency offset. The UE transmits, to the network entity, at least one uplink channel with no phase continuity based on the determination to not apply phase continuity to the UL transmissions.

Abstract: An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

Abstract: The present application provides a time synchronization method and an electronic device. The method includes sending a clock synchronization signal and first real time clock (RTC) information separately; and the clock synchronization signal is configured to measure a delay between a first module and at least one second module, the delay is used for phase compensation performed on the clock synchronization signal received at the side of the at least one second module, and the clock synchronization signal after being subjected to the phase compensation is configured to trigger the at least one second module to update local second RTC information to the first RTC information.

Abstract: The present disclosure relates to a parallel filter structure for processing a signal. The parallel filter structure includes a signal input configured to receive a time and value discrete input signal. The parallel filter structure includes a feed forward equalizer circuit connected with the signal input for receiving the time and value discrete input signal. The parallel filter structure includes a decision feedback equalizer circuit connected with the signal input for receiving the time and value discrete input signal. The feed forward equalizer circuit and the decision feedback equalizer circuit together form a parallel circuit. Further, an oscilloscope and a method of processing a signal are provided.

Abstract: A device includes a decoder configured to receive an input signal. The decoder is configured to also output a control signal based on the input signal. The device further includes an equalizer configured to receive a distorted bit as part of a data stream, receive the control signal, select a distortion correction factor based upon the control signal, apply the distortion correction factor to the distorted bit to offset inter-symbol interference from the data stream on the distorted input data to generate a modified value of the distorted bit, and generate a corrected bit based on the modified value of the distorted bit.

Abstract: A transmission apparatus that (i) generates a Quadrature Phase Shift Keying (QPSK) modulation signal s1(t) by applying a QPSK modulation scheme to a first data sequence, (ii) generates a 16-Quadrature Amplitude Modulation (QAM) modulation signal s2(t) by applying a 16-QAM modulation scheme to a second data sequence, (iii) generates a transmission signal z1(t) and a second transmission signal z2(t) by applying a phase hopping process, a precoding process, and a power adjust process to the QPSK modulation signal s1(t) and the 16-QAM modulation signal s2(t), wherein an average transmission power of the 16-QAM modulation signal s2(t) being the same as an average transmission power of the QPSK modulation signal s1(t), and (iv) transmits the transmission signal z1(t) from a first antenna at a first time and a first frequency and the second transmission signal z2(t) from a second antenna at the first time and the first frequency.

Abstract: A method executable by a low voltage drive circuit (LVDC) includes receiving an analog receive signal, converting the analog receive signal into analog inbound data, converting the analog inbound data into digital inbound data, filtering the digital inbound data to produce filtered digital data, sampling and holding an n-bit digital value of the filtered digital data to produce an n-bit sampled digital data value, adjusting formatting of the n-bit sampled digital data value to produce a formatted digital value, and generating a packet of received digital data from a plurality of formatted digital values.

Abstract: Various embodiments provide for a data sampler with built-in decision feedback equalization (DFE) and offset cancellation. For some embodiments, two or more data samplers described herein can be used to implement a data signal receiver circuit, which can use those two or more data samplers to facilitate half-rate or quarter-rate data sampling.