Abstract: An assembly for a vehicle includes a steering wheel. The assembly includes an airbag inflatable to an inflated position. The airbag has a main chamber supported by the steering wheel. The main chamber in the inflated position has a rear panel facing the steering wheel, an impact panel opposite the rear panel, and an outermost periphery between the impact panel and the rear panel. The airbag includes an extension having a first end and a terminal end. The extension extends from the first end to the terminal end adjacent the rear panel of the main chamber. The first end extends from the outermost periphery and the rear panel and the terminal end is connected to the rear panel. The airbag has an inflation chamber extending from the main chamber to the terminal end through the first end of the extension.

Abstract: A quick coupling set includes a socket and a mating plug. The socket has a rotation-restraining structure while the mating plug has a mating rotation-restraining structure. In the coupling of the socket and the mating plug, the rotation-restraining structure of the socket only allow the rotation-restraining structure of the mating plug to relatively rotate in a rotation direction, so as to complete the coupling of the socket and the mating plug. Other plugs which do not match the socket lack of a rotation-restraining structure matching that of the socket, and cannot relatively rotate in the rotation direction with respect to the socket and cannot achieve any coupling with the socket, which results in the socket and the mating plug being protected against misconnection.

Abstract: A package applied to a flyback power converter includes a first lead frame and a second lead frame. The first lead frame connects to at least one component of a primary side of the flyback power converter. An isolation distance exists between the first lead frame and the second lead frame. The primary side of the flyback power converter is galvanically isolated from and communicates with a secondary side of the flyback power converter through capacitive coupling effect between the first lead frame and the second lead frame.

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

Abstract: A home user interface (UI) system for managing digital ink is provided. The home UI system includes a plurality of state sensors capable of detecting a state in a house or a change in the state, and a plurality of home-use devices that are provided in the house or that form part of the house and that each include a handwriting sensor capable of detecting handwriting made by a person. The home UI system further includes one or more notification units that are configured to notify the person of the existence of the home-use device or a detectable region of the handwriting sensor of the home-use device. The home UI system further includes a controller which, when it is determined that a notification is necessary from a detection result of one or more of the state sensors, instructs at least one of the notification units to carry out the notification.

Abstract: Memory cells and methods of forming the same include forming a hole in an interlayer dielectric to expose an end of a conductive top electrode. A phase change material is conformally deposited on surfaces of the hole. A remaining portion of the hole is filled with a dielectric material after conformally depositing the phase change material.

Abstract: A method for training an autoencoder implemented in an electronic device includes obtaining a stereoscopic image as the vehicle is in motion, the stereoscopic image includes a left image and a right image; generating a stereo disparity map according to the left image; generating a predicted right image according to the left image and the stereo disparity map; and calculating a first mean square error between the predicted right image and the right image.

Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.

Abstract: A power module includes two power input terminals, two main substrates, a plurality of first switches, a plurality of second switches, and a bridge main unit. The bridge main unit is across the two main substrates, and includes a first bridge subunit and a second bridge subunit. Each of the first bridge subunit and the second bridge subunit includes a first conducting region on a bottom surface, and a second conducting region and a third conducting region on a top surface. The first conducting region transmits a current signal of a current path of a switch circuit formed by the power input terminals, the first switches, and the second switches. The second conducting region is connected to the control terminals of the first switches and the second switches. The third conducting region is connected to the output terminals of the first switches and the second switches.

Abstract: A method for detecting medical images implemented in an electronic device includes obtaining at least one image to be detected; obtaining a reconstructed image by inputting the at least one image to be detected as a target image into a pre-trained variational autoencoder model; determining a target area according to pixel values of pixels in the reconstructed image and the target image; obtaining a feature area and a lesion category of the feature area by inputting the target image into a pre-trained convolutional neural network model; when there is a feature area corresponding to the target area in the target image, determining a lesion area and a corresponding lesion category based on the target area and the feature area, and generating a detection result of the image to be detected.

Abstract: Disclosed is a flip-chip packaged power transistor module having a built-in gate driver, for outputting a high-power signal of at least tens of amperes, the module including at least one power transistor die which has an active side where at least one source pin, at least one drain pin and at least one gate pin are exposed; a ceramic substrate body which has a conducting junction side and a heat spreading side, a minimal spacing of the gate bonding pad from at least one of the source bonding pad or the drain bonding pad being less than 500 ?m, whereby parasitic inductance generated therebetween is reduced; at least one gate driver which has at least one gate pin configured to be soldered to the gate bonding pad, and at least one gate drive pin which corresponds to the gate pin and is configured to be soldered to the drive bonding pad.

Abstract: In some embodiments, the present disclosure relates to a method that includes bonding a first wafer to a second wafer to form a wafer stack and removing a top portion of the second wafer. A first trim blade having a first blade width is aligned over the second wafer. The first trim blade is used to form a trench that separates a central portion of the second wafer from a peripheral portion of the second wafer. The trench is arranged at a first distance from an outer perimeter of the second wafer, and extends from a top surface of the second wafer to a trench depth beneath the top surface of the first wafer. A second trim blade having a second blade width is aligned over the peripheral portion, the second blade width being greater than the first blade width. The peripheral portion is removed using the second trim blade.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed within a dielectric structure on a substrate, and a second via disposed within the dielectric structure and laterally separated from the first via by the dielectric structure. The first via has a first width that is smaller than a second width of the second via. An interconnect wire vertically contacts the second via and extends laterally past an outermost sidewall of the second via. A through-substrate via (TSV) is arranged over the second via and extends through the substrate. The TSV has a minimum width that is smaller than the second width of the second via. The second via has opposing outermost sidewalls that are laterally outside of the TSV.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes bonding a first semiconductor wafer to a second semiconductor wafer. A bond interface is disposed between the first and second semiconductor wafers. The first semiconductor wafer has a peripheral region laterally surrounding a central region. A support structure is formed between a first outer edge of the first semiconductor wafer and a second outer edge of the second semiconductor wafer. The support structure is disposed within the peripheral region. A thinning process is performed on the second semiconductor wafer.

Abstract: An apparatus, semiconductor device and method of manufacture are presented, wherein a hard mask layer and one or more etch stop layers are etched in an etching chamber. In an embodiment the semiconductor device is placed on a mounting platform at a first height and an etch process is performed, then the semiconductor device is moved to a second height within the chamber and a second etch process is performed, with the rotational speed of the semiconductor device reduced during movements in order to reduce the chance of cross contamination.

Abstract: A structure including an inner electrode and an outer electrode on a substrate and a phase change material layer, the phase change material layer vertically aligned above both the inner electrode and the outer electrode. A structure including an inner electrode and an outer electrode on a substrate and a phase change material layer, the phase change material layer vertically aligned above both the inner electrode and the outer electrode, where the inner electrode and the outer electrode are on the same horizontal plane. A method including forming an inner electrode and an outer electrode simultaneously on a substrate, forming a phase change material layer above both the inner electrode and the outer electrode.

Abstract: A secondary-side control method of a flyback power converter includes a primary controller included in the flyback power converter generating a first gate control signal to turn on a power switch at a first predetermined valley of a first voltage after the primary controller enters a start-up mode; and a secondary controller included in the flyback power converter generating a trigger pulse to a synchronous switch at a second predetermined valley of a second voltage to make the primary controller enter a secondary-side control mode from the start-up mode after the secondary controller detects a first coupling voltage corresponding to the first gate control signal on the second voltage.