Abstract: In some embodiments, the present disclosure relates to method of forming an integrated circuit, including forming a semiconductor device on a frontside of a semiconductor substrate; depositing a dielectric layer over a backside of the semiconductor substrate; patterning the dielectric layer to form a first opening in the dielectric layer so that the first opening exposes a surface of the backside of the semiconductor substrate; depositing a glue layer having a first thickness over the first opening; filling the first opening with a first material to form a backside contact that is separated from the semiconductor substrate by the glue layer; and depositing more dielectric layers, bonding contacts, and bonding wire layers over the dielectric layer to form a second bonding structure on the backside of the semiconductor substrate, so that the backside contact is coupled to the bonding contacts and the bonding wire layers.

Abstract: In some embodiments, the present disclosure relates to a 3D integrated circuit (IC) stack that includes a first IC die bonded to a second IC die. The first IC die includes a first semiconductor substrate, a first interconnect structure arranged on a frontside of the first semiconductor substrate, and a first bonding structure arranged over the first interconnect structure. The second IC die includes a second semiconductor substrate, a second interconnect structure arranged on a frontside of the second semiconductor substrate, and a second bonding structure arranged on a backside of the second semiconductor substrate. The first bonding structure faces the second bonding structure. Further, the 3D IC stack includes a first backside contact that extends from the second bonding structure to the backside of the second semiconductor substrate and is thermally coupled to at least one of the first or second interconnect structures.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a standard contact disposed within a dielectric structure on a substrate. An oversized contact is disposed within the dielectric structure and is laterally separated from the standard contact. The oversized contact has a larger width than the standard contact. An interconnect wire vertically contacts the oversized contact. A through-substrate via (TSV) vertically extends through the substrate. The TSV physically and vertically contacts the oversized contact or the interconnect wire. The TSV vertically overlaps the oversized contact or the interconnect wire over a non-zero distance.

Abstract: A first phase change material layer vertically aligned above a bottom electrode, a dielectric layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the dielectric layer, an inner electrode physically and electrically connected to the first phase change material layer and the second phase change material layer, the inner electrode surrounded by the dielectric layer, a top electrode vertically aligned above the second phase change material layer. A first phase change material layer vertically aligned above a bottom electrode, a filament layer vertically aligned above the first phase change material layer, a second phase change material layer vertically aligned above the filament layer, an inner break in the filament layer connecting the first phase change material layer and the second phase change material layer, a top electrode vertically aligned above the second phase change material layer.

Abstract: Provided is a method for fabricating an interconnect. The method comprises forming a topological semi-metal layer. The method further comprises patterning the topological semi-metal layer to form one or more interconnects. The method further comprises forming a dielectric layer between the one or more interconnects. The method further comprises forming a hermetic dielectric cap layer on top of the one or more interconnects and the dielectric layer.

Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

Abstract: A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.

Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.

Abstract: A wearable display device is disclosed and includes a main body and a driving module. The main body includes a frame, two temple arms and at least one monitor. The two temple arms are respectively connected with two ends of the frame, and the monitor is disposed on the frame. The driving module is disposed within the frame and includes a microprocessor, an optical display module and a heat dissipation component. The optical display module is electrically coupled with the microprocessor and configured for displaying an optical image on the at least one monitor. The heat dissipation component includes a heat dissipation base and two heat pipes. The two heat pipes are disposed on the heat dissipation base adjacent to the microprocessor. When the heat generated by the microprocessor is conducted to the heat dissipation base, the two heat pipes perform heat exchange with the heat dissipation base.

Abstract: A hair treatment method including applying to a scalp a cosmetic composition comprising the following components (A), (B) and (C) and having a viscosity of from 1 to 30,000 mPa·s at pH 4.1: (A) a pH buffer; (B) an antioxidant; and (C) a pH-responsive thickener. The method further includes applying to the hair at least one hair treatment agent composition selected from the group consisting of a hair color composition, a hair bleach composition, a perm composition and a relaxer composition.

Abstract: A position indicator that is used with a position detection device including a position detection sensor, the position indicator including a first function module and a second function module. The first function module includes a core body that, in operation, is brought into contact with an input surface for position detection in the position detection sensor, and a position detection signal transmission circuit, in operation, that transmits a position detection signal to the position detection sensor. The second function module includes a first function circuit that, in operation, generates characteristic selection information corresponding to a characteristic of the core body or a characteristic of the input surface and transmits the characteristic selection information, or a second function circuit that, in operation, generates a stimulus corresponding to the characteristic selection information such that a user who is holding the position indicator audibly or tactilely perceives the stimulus.

Abstract: A low parasitic inductance power module featuring staggered interleaving conductive members, including: at least one base extending in a length direction; a substrate on which at least one input bus bar and at least one output bus bar are provided; a first unit including a first circuit base portion disposed on the base in a width direction, a plurality of first power devices being disposed on the first circuit base portion, each first power device having a first current input end and a first current output end which are parallel connected, the first current input end or the first current output end being conducted to the first circuit base portion; and a second unit. The units are serially-connected to the bus bars via input conductive members and output conductive members arrayed in a staggered interleaving mode, whereby to create individual inductances counteracting with each other, reducing overall parasitic inductance.

Abstract: In some embodiments, the present disclosure relates to method of forming an integrated circuit, including forming a semiconductor device on a frontside of a semiconductor substrate; depositing a dielectric layer over a backside of the semiconductor substrate; patterning the dielectric layer to form a first opening in the dielectric layer so that the first opening exposes a surface of the backside of the semiconductor substrate; depositing a glue layer having a first thickness over the first opening; filling the first opening with a first material to form a backside contact that is separated from the semiconductor substrate by the glue layer; and depositing more dielectric layers, bonding contacts, and bonding wire layers over the dielectric layer to form a second bonding structure on the backside of the semiconductor substrate, so that the backside contact is coupled to the bonding contacts and the bonding wire layers.

Abstract: Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. A control circuit includes a first transistor, an inverter coupled to the first transistor, and a second transistor comprising a gate, a first source/drain terminal and a second source/drain terminal. The second transistor is coupled to the inverter. The first source/drain terminal of the second transistor is coupled in series to the first transistor. The second source/drain terminal is coupled to a decoder driver circuit. The second transistor is configured to charge a load of a common decoder line so as to reduce an effective load of the decoder driver circuit.

Abstract: The present disclosure relates to a semiconductor wafer structure including a semiconductor substrate and a plurality of semiconductor devices disposed along the semiconductor substrate. A dielectric stack including a plurality of dielectric layers is arranged over the semiconductor substrate. A conductive interconnect structure is within the dielectric stack. A seal ring layer is over the dielectric stack and laterally surrounds the dielectric stack along a first sidewall of the dielectric stack. The seal ring layer includes a first protrusion that extends into a first trench in the semiconductor substrate.

Abstract: A phase change memory includes a phase change structure. There is a heater coupled to a first surface of the phase change structure. A first electrode is coupled to a second surface of the phase change structure. A second electrode coupled to a second surface of the heater. A third electrode is connected to a first lateral end of the phase change structure and a fourth electrode connected to a second lateral end of the phase change structure.

Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: A method comprising identifying a set of target features for a plurality of data instances of an input data collection; determining feature values for the set of target features for the plurality of data instances; identifying a plurality of outlier data instances based on the determined feature values; identifying a plurality of noisy data instances from the outlier data instances based on feature values of the plurality of noisy data instances, wherein a noisy data instance is identified based on a determination that noise is present in noisy data instance; and providing an indication of the plurality of noisy data instances.

Abstract: A hair dryer comprises a fan, a heater, a temperature sensor, and a controller. The heater is disposed at the airflow output end of the fan and used to heat the airflow output by the fan. The temperature sensor is pointed to the hair, receiving the infrared light radiated by the hair to obtain the temperature of the hair, determining the dryness of the hair according to at least one of the temperature of the hair and the rate of temperature variation of the hair, and outputting a corresponding control signal. The controller is electrically connected with the fan, the heater and the temperature sensor, and controlling at least one of the rotation speed of the fan and the heating power of the heater according to the control signal. The above-mentioned hair dryer not only can prevent from hair overheating and hair damage but also can shorten the time for drying hair.