Patents by Inventor Afshin Momtaz
Afshin Momtaz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9077328Abstract: Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal.Type: GrantFiled: April 7, 2014Date of Patent: July 7, 2015Assignee: Broadcom CorporationInventors: Magesh Valliappan, Afshin Momtaz, Namik Kocaman, Vasudevan Parthasarathy
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Publication number: 20150180649Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.Type: ApplicationFiled: March 3, 2015Publication date: June 25, 2015Inventors: Mahmoud Reza AHMADI, Siavash FALLAHI, Tamer ALI, Ali NAZEMI, Hassan MAAREFI, Burak CATLI, Afshin MOMTAZ
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Patent number: 9024659Abstract: A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.Type: GrantFiled: November 5, 2013Date of Patent: May 5, 2015Assignee: Broadcom CorporationInventors: Tamer Ali, Hassan Maarefi, Mahmoud Reza Ahmadi, Afshin Momtaz
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Patent number: 9001869Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.Type: GrantFiled: July 19, 2013Date of Patent: April 7, 2015Assignee: Broadcom CorporationInventors: Mahmoud Reza Ahmadi, Siavash Fallahi, Tamer Ali, Ali Nazemi, Hassan Maarefi, Burak Catli, Afshin Momtaz
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Publication number: 20150092829Abstract: A device for passive equalization and slew-rate control of a signal includes a first branch that includes a first driver coupled in series with an equalization capacitor, and a second branch that includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch, and the first branch may be configurable to enable one of passive equalization or slew-rate control of the signal based on a mode control signal.Type: ApplicationFiled: November 5, 2013Publication date: April 2, 2015Applicant: Broadcom CorporationInventors: Tamer ALI, Hassan Maarefi, Mahmoud Reza Ahmadi, Afshin Momtaz
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Patent number: 8964907Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.Type: GrantFiled: April 26, 2013Date of Patent: February 24, 2015Assignee: Broadcom CorporationInventors: Vivek Pundlik Telang, Hong Chen, Vasudevan Parthasarathy, Jun Cao, Afshin Momtaz, Ali Ghiasi, Chung-Jue Chen
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Patent number: 8964923Abstract: Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies.Type: GrantFiled: June 24, 2011Date of Patent: February 24, 2015Assignee: Broadcom CorporationInventors: Anand Jitendra Vasani, Jun Cao, Afshin Momtaz
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Patent number: 8958501Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.Type: GrantFiled: December 19, 2012Date of Patent: February 17, 2015Assignee: Broadcom CorporationInventors: Ali Nazemi, Mahmoud Reza Ahmadi, Tamer Ali, Bo Zhang, Mohammed Abdul-Latif, Namik Kocaman, Afshin Momtaz
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Patent number: 8948237Abstract: An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.Type: GrantFiled: January 4, 2013Date of Patent: February 3, 2015Assignee: Broadcom CorporationInventors: Namik Kemal Kocaman, Afshin Momtaz, Velu Chellam Pillai, Vivek Telang, Sundararajan Chidambara, Magesh Valliappan
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Patent number: 8947167Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.Type: GrantFiled: June 28, 2013Date of Patent: February 3, 2015Assignee: Broadcom CorporationInventors: Mahyar Kargar, Siavash Fallahi, Namik Kocaman, Mehdi Khanpour, Afshin Momtaz
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Publication number: 20150010044Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.Type: ApplicationFiled: September 26, 2014Publication date: January 8, 2015Inventors: Heng Zhang, Mehdi Khanpour, Jun Cao, Chang Liu, Afshin Momtaz
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Patent number: 8928355Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.Type: GrantFiled: April 22, 2013Date of Patent: January 6, 2015Assignee: Broadcom CorporationInventors: Delong Cui, Afshin Momtaz, Jun Cao
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Patent number: 8913706Abstract: A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency.Type: GrantFiled: August 20, 2010Date of Patent: December 16, 2014Assignee: Broadcom CorporationInventors: Jun Cao, Afshin Momtaz, Chung-Jue Chen, Kang Xiao, Vivek Telang, Ali Ghiasi
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Patent number: 8873606Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.Type: GrantFiled: November 7, 2012Date of Patent: October 28, 2014Assignee: Broadcom CorporationInventors: Heng Zhang, Mehdi Khanpour, Jun Cao, Chang Liu, Afshin Momtaz
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Patent number: 8836553Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.Type: GrantFiled: January 30, 2013Date of Patent: September 16, 2014Assignee: Broadcom CorporationInventors: Bo Zhang, Ali Nazemi, Mahmoud Reza Ahmadi, Afshin Momtaz, Heng Zhang, Hassan Maarefi
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Publication number: 20140241442Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.Type: ApplicationFiled: July 19, 2013Publication date: August 28, 2014Inventors: Mahmoud Reza Ahmadi, Siavash Fallahi, Tamer Ali, Ali Nazemi, Hassan Maarefi, Burak Catli, Afshin Momtaz
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Publication number: 20140153680Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Applicant: BROADCOM CORPORATIONInventors: Adesh Garg, Jun Cao, Namik Kocaman, Kuo-J Huang, Delong Cui, Afshin Momtaz
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Publication number: 20140146922Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.Type: ApplicationFiled: December 19, 2012Publication date: May 29, 2014Applicant: BROADCOM CORPORATIONInventors: Ali Nazemi, Mahmoud Reza Ahmadi, Tamer Ali, Bo Zhang, Mohammed Abdul-Latif, Namik Kocaman, Afshin Momtaz
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Patent number: 8731098Abstract: A transmitting system includes a clock system and a data system. The clock system is configured to receive a clock having a first value and produce a control signal having a second, different value and an output clock having the first value. The data system is configured to receive data and the control signal and to align the data with the output clock, based on the control signal, to produce output data. The clock system includes a driver configured to produce the output clock, a divider configured to divide the received clock, and a phase interpolator configured to rotate the divided clock to produce the control signal. Also, the data is parallel data, and the data system includes a multiplexer configured to receive the parallel data and to use the control signal to serialize the parallel data as the aligned data and a driver configured to produce the output data.Type: GrantFiled: September 15, 2010Date of Patent: May 20, 2014Assignee: Broadcom CorporationInventors: Delong Cui, Afshin Momtaz, Jun Cao
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Patent number: RE45557Abstract: A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.Type: GrantFiled: July 3, 2013Date of Patent: June 9, 2015Assignee: Broadcom CorporationInventors: Mario Caresosa, Namik Kocaman, Afshin Momtaz