Patents by Inventor Akihiro Yamazaki

Akihiro Yamazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5699297
    Abstract: The present invention relates to a method of rewriting data in a microcomputer additionally provided with a flash memory having a refresh mode, in which the data retained in an area arbitrarily specified in the flash memory is transferred to a RAM for temporary evacuation and after the data in the area has been erased, the data evacuated to the flash memory is written into the area again.
    Type: Grant
    Filed: May 29, 1996
    Date of Patent: December 16, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Yamazaki, Takamichi Kasai
  • Patent number: 5579270
    Abstract: A non-volatile semiconductor memory with an auto-function for automatically writing or erasing data includes a logic circuit, a select circuit and a test-mode control section. The test-mode control section responds to a plurality of signals transmitted from the outside of the memory for outputting a second verify signal indicating that a verify result is normal, a third verify signal indicating that the verify result is abnormal, and a select signal for selecting an external clock signal from the outside of the memory. The logic circuit forcibly sets to a predetermined value a first verify signal output from a verify circuit on the basis of the second and third verify signals output from the test-mode control section. The select circuit selects, in a normal mode, a clock signal output from an oscillator, and selects, in a test mode, the external clock signal. The number of repetitions of retrial is set irrespective of the verify signal output from the verify circuit.
    Type: Grant
    Filed: April 25, 1995
    Date of Patent: November 26, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akihiro Yamazaki
  • Patent number: 5515323
    Abstract: A memory cell array is constructed by electrically programmable non-volatile memory cells. A memory peripheral circuit creates an address signal for designating an address in the memory cell array by means of the row decoder and the column decoder to effect the access operation for the memory cell array. An ATD circuit for generating a control signal which permits selection of the memory cell involved in the access operation in the memory cell array for a preset period of time in response to a variation of the address signal is provided. A latch circuit for latching readout data from the memory cell in an active period of the control signal is provided. That is, all of the memory cells in the memory cell array are set in the non-selected state in a period other than the active period of the control signal.
    Type: Grant
    Filed: January 23, 1995
    Date of Patent: May 7, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Yamazaki, Toru Okawa
  • Patent number: 5500286
    Abstract: A multi-shell emulsion particle of dry state structure having one or more of penetrating pore(s) connecting the surface layer of the particle with the interior of the particle and having a particle diameter of from 0.1 to 5.0.mu. preferably from 0.1 to 1.2.mu..
    Type: Grant
    Filed: November 18, 1994
    Date of Patent: March 19, 1996
    Assignee: Mitsui Toatsu Chemicals, Incorporated
    Inventors: Kousuke Someya, Akihiro Yamazaki, Futoshi Hoshino, Takeshi Yanagihara
  • Patent number: 5409776
    Abstract: A multi-shell emulsion particle of dry state structure having one or more of penetrating pore(s) connecting the surface layer of the particle with the interior of the particle and having a particle diameter of from 0.1 to 5.0.mu. preferably from 0.1 to 1.2.mu..
    Type: Grant
    Filed: February 1, 1994
    Date of Patent: April 25, 1995
    Assignee: Mitsui Tomatsu Chemicals, Incorporated
    Inventors: Kousuke Someya, Akihiro Yamazaki, Futoshi Hoshino, Takeshi Yanagihara
  • Patent number: 5307313
    Abstract: In a semiconductor integrated circuit for switching various functions in accordance with "H"/"L" level of a read output from EPROM cells or the like, a state of memory cells incorporated in the semiconductor is detected to switch a function state. The semiconductor integrated circuit is free from an inoperative state caused by indefinite values of an initial state (erasure state) as of the EPROM cells and the like, or is free from a state in which only a predetermined operation is performed. When a writing operation is performed to EPROM cells and the like in an initial state in advance, a function test for a semiconductor integrated circuit can be normally performed. A test time can be largely decreased compared with that of a conventional technique, and a production cost can be largely reduced.
    Type: Grant
    Filed: February 22, 1991
    Date of Patent: April 26, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Yamazaki, Tomotaka Saito, Shuichi Ito
  • Patent number: 5273824
    Abstract: A cored multi-shell emulsion particle consisting of a core particle, a void layer existing in the exterior of the core particle and a shell layer, each of which has a diameter of .phi., d and D, respectively, and the ratio of .phi., d and D is in the following range..phi./D=0.1-0.6d/D=0.2-0.8 (d>.phi.)The particle exhibits excellent hiding power, brightness, gloss and thermal insulation property as an organic pigment without impairing drying ability and strength of coated layer.
    Type: Grant
    Filed: February 1, 1991
    Date of Patent: December 28, 1993
    Assignee: Mitsui Toatsu Chemicals, Incorporated
    Inventors: Futoshi Hoshino, Makoto Nakano, Kousuke Someya, Junko Morita, Takeshi Yanagihara, Akihiro Yamazaki
  • Patent number: 5210066
    Abstract: A heat-sensitive recording material wherein a copolymer emulsion is employed, the copolymer emulsion being obtained by copolymerizing a monomer component which comprises (meth)acrylamide and an optional unsaturated monomer component copolymerizable with (meth)acrylamide in the presence of a seed emulsion serving as a nucleating particle. In the heat-sensitive recording material, the intermediate layer, the heat-sensitive recording layer or the protective layer comprises the copolymer emulsion. The recordinq layer and the resulting recorded images of such a heat-sensitive recording material have sufficient durability (such as water resistance, heat resistance, resistance to plasticizers and resistance to solvents) and the resistance to heat softening of the protective layer. The heat-sensitive recording material can be produced through easy process control and is excellent in color developing sensitivity.
    Type: Grant
    Filed: December 21, 1990
    Date of Patent: May 11, 1993
    Assignee: Mitsui Toatsu Chemicals, Inc.
    Inventors: Shinziro Sakurai, Akihiro Yamazaki, Takeshi Yanagihara, Makoto Nakano, Masaya Kusumoto
  • Patent number: 5138190
    Abstract: A charge pump circuit including a step-up section (1) having an output point to which a load is connected, the step-up section (1 ) having a function to step up an output potential from a predetermined potential lower than a potential (V.sub.PP) of a power supply to a desired potential higher than the power supply potential (V.sub.PP), wherein the charge pump circuit comprises initial potential setting switch (N.sub.10) connected between the power supply and the output point of the step-up section (1), and operative so that it is turned on with the beginning of the step-up operation of the step-up section (1) to propagate the power supply potential (V.sub.PP) to the output point of the step-up section (1), and that it is turned off in a suitable time. With the beginning of the step-up operation of the step-up section (1), the initial potential setting switch (N.sub.10) is turned on. As a result, a power supply potential (V.sub.PP) is propagated to the output point of the step-up section (1).
    Type: Grant
    Filed: September 12, 1989
    Date of Patent: August 11, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Yamazaki, Tomotaka Saito
  • Patent number: 5016218
    Abstract: In a nonvolatile memory of the present invention, a write circuit is connected between bit lines and a write-enable voltage terminal and has at least two write MOS transistors connected to each other in a serial manner. Since at least two write MOS transistors are connected in a serial manner, a punch-through effect is reduced even if noises occur in a write voltage system. Even in the case where a punch-through effect occurs due to the presence of a power source and transistors, a voltage on the bit line is reduced, thus preventing a write error from occurring relative to the memory cell transistors.
    Type: Grant
    Filed: November 21, 1988
    Date of Patent: May 14, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Yamazaki, Katsuya Kiyohara
  • Patent number: 4973975
    Abstract: One of analog input voltages applied to a plurality of analog input terminals is selected by means of analog switches connected to the respective analog input terminals and supplied to a common terminal. In this case, each of the analog switches permits selective supply of the potential of a corresponding one of the plurality of analog input terminals in response to a control signal supplied from a controller. The common terminal is connected to the positive input terminal of a comparator. The comparator compares the voltage with a digital output value from the controller which is converted into an analog voltage by means of a D/A converter. Further, the controller generates a preset control signal in an inhibition period during which supply of a voltage from the plurality of analog input terminals to the common terminal is inhibited.
    Type: Grant
    Filed: August 8, 1989
    Date of Patent: November 27, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Yamazaki, Tomotaka Saito, Hideo Sakai
  • Patent number: 4371613
    Abstract: Purine-arabinosides and a method for making purine-arabinosides are disclosed. The method comprises contacting an arabinose donor and a purine source in the presence of an effective amount of enzyme produced by a bacterium and capable of transarabinosylation from the arabinose donor to the purine source, whereby a 9-(.beta.-D-arabinofuranosyl)-purine is produced.
    Type: Grant
    Filed: August 1, 1978
    Date of Patent: February 1, 1983
    Assignee: Ajinomoto Company Incorporated
    Inventors: Takashi Utagawa, Takeshi Miyoshi, Hirokazu Morisawa, Akihiro Yamazaki, Fumihiro Yoshinaga, Koji Mitsugi
  • Patent number: 4186266
    Abstract: 5-Fluorouraacil is produced by reacting orotic acid with a fluorinating agent and then, decarboxylating the resulting 5-fluoro-orotic acid.
    Type: Grant
    Filed: June 7, 1978
    Date of Patent: January 29, 1980
    Assignees: Asahi Glass Company Limited, Ajinomoto Company Incorporated
    Inventors: Akihiro Yamazaki, Hirokazu Morisawa, Yoshio Oda, Keiichi Uchida