Patents by Inventor Akio Nakagawa
Akio Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140319576Abstract: In a non-punch-through (NPT) insulated gate bipolar transistor (IGBT), a rear surface structure including a p+ collector layer and a collector electrode is provided on a rear surface of an n? semiconductor substrate and a depletion layer which is spread from a pn junction between a p base region and an n? drift layer when the NPT-IGBT is turned off does not come into contact with the p+ collector layer. A carrier concentration of a region of the n? drift layer that is provided at a depth of 0.3 ?m or less from a pn junction between the n? drift layer and the p+ collector layer is in the range of 30% to 70% of a stored carrier concentration of a region of the n? drift layer that is provided at a depth greater than 0.3 ?m from the pn junction.Type: ApplicationFiled: July 9, 2014Publication date: October 30, 2014Applicant: FUJI ELECTRIC CO., LTD.Inventors: Yusuke KOBAYASHI, Manabu Takei, Akio Nakagawa
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Patent number: 8854033Abstract: A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell.Type: GrantFiled: June 1, 2011Date of Patent: October 7, 2014Assignee: DENSO CORPORATIONInventors: Satoshi Shiraki, Norihito Tokura, Shigeki Takahashi, Masahiro Yamamoto, Akira Yamada, Hiroyasu Kudo, Youichi Ashida, Akio Nakagawa
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Publication number: 20140240015Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: ApplicationFiled: May 7, 2014Publication date: August 28, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Kazutoshi NAKAMURA, Toru TAKAYAMA, Yuki KAMATA, Akio NAKAGAWA, Yoshinobu SANO, Toshiyuki NAKA
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Publication number: 20140225234Abstract: A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.Type: ApplicationFiled: April 22, 2014Publication date: August 14, 2014Applicant: DENSO CORPORATIONInventors: Takao YAMAMOTO, Norihito TOKURA, Hisato KATO, Akio NAKAGAWA
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Patent number: 8791690Abstract: A semiconductor device having a lateral semiconductor element includes a semiconductor substrate, a first electrode on the substrate, a second electrode on the substrate, and an isolation structure located in the substrate to divide the substrate into a first island and a second island electrically insulated from the first island. The lateral semiconductor element includes a main cell located in the first island and a sense cell located in the second island. The main cell causes a first current to flow between the first electrode and the second electrode so that the first current flows in a lateral direction along the surface of the substrate. The first current is detected by detecting a second current flowing though the sense cell.Type: GrantFiled: June 1, 2011Date of Patent: July 29, 2014Assignee: DENSO CORPORATIONInventors: Satoshi Shiraki, Norihito Tokura, Shigeki Takahashi, Masahiro Yamamoto, Akira Yamada, Hiroyasu Kudo, Youichi Ashida, Akio Nakagawa
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Patent number: 8760206Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: GrantFiled: June 11, 2013Date of Patent: June 24, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Patent number: 8742534Abstract: A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.Type: GrantFiled: August 3, 2011Date of Patent: June 3, 2014Assignee: DENSO CORPORATIONInventors: Takao Yamamoto, Norihito Tokura, Hisato Kato, Akio Nakagawa
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Publication number: 20140132979Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.Type: ApplicationFiled: January 16, 2014Publication date: May 15, 2014Applicant: CANON KABUSHIKI KAISHAInventors: Akio Nakagawa, Hisashi Ishikawa
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Patent number: 8707132Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.Type: GrantFiled: July 1, 2011Date of Patent: April 22, 2014Assignee: Canon Kabushiki KaishaInventors: Akio Nakagawa, Hisashi Ishikawa
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Publication number: 20140070271Abstract: A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.Type: ApplicationFiled: November 12, 2013Publication date: March 13, 2014Applicant: DENSO CORPORATIONInventors: Shigeki TAKAHASHI, Norihito TOKURA, Satoshi SHIRAKI, Youichi ASHIDA, Akio NAKAGAWA
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Publication number: 20130270910Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: ApplicationFiled: June 11, 2013Publication date: October 17, 2013Inventors: Kazutoshi NAKAMURA, Toru TAKAYAMA, Yuki KAMATA, Akio NAKAGAWA, Yoshinobu SANO, Toshiyuki NAKA
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Patent number: 8497720Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: GrantFiled: June 20, 2012Date of Patent: July 30, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Patent number: 8411988Abstract: An image processing apparatus partitions entered image data into first partitioned image data and appends margin data to the first partitioned image data. The image processing apparatus corrects the first partitioned image data other than the margin data to second partitioned image data and processes the second partitioned image data and the margin data.Type: GrantFiled: July 24, 2008Date of Patent: April 2, 2013Assignee: Canon Kabushiki KaishaInventors: Akio Nakagawa, Hisashi Ishikawa
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Patent number: 8354691Abstract: A N-channel lateral insulated-gate bipolar transistor includes a semiconductor substrate, a drift layer, a collector region, a channel layer, an emitter region, a gate insulation film, a gate electrode, a collector electrode, an emitter electrode. The collector region includes a high impurity concentration region having a high impurity concentration and a low impurity concentration region having a lower impurity concentration than the high impurity concentration region. The collector electrode is in ohmic contact with the high impurity concentration region and in schottky contact with the low impurity concentration region.Type: GrantFiled: September 7, 2011Date of Patent: January 15, 2013Assignee: DENSO CORPORATIONInventors: Norihito Tokura, Shigeki Takahashi, Youichi Ashida, Akio Nakagawa
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Publication number: 20120256607Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: ApplicationFiled: June 20, 2012Publication date: October 11, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kazutoshi NAKAMURA, Toru TAKAYAMA, Yuki KAMATA, Akio NAKAGAWA, Yoshinobu SANO, Toshiyuki NAKA
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Patent number: 8248128Abstract: A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.Type: GrantFiled: May 19, 2011Date of Patent: August 21, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Kazutoshi Nakamura, Toru Takayama, Yuki Kamata, Akio Nakagawa, Yoshinobu Sano, Toshiyuki Naka
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Publication number: 20120119318Abstract: In a semiconductor device in which a first electrode and a second electrode are disposed on a surface of a first conductivity-type semiconductor layer of a semiconductor substrate and a lateral element is formed to cause an electric current between the first electrode and the second electrode, a scroll-shaped resistive field plate is disposed on the semiconductor layer across an insulation film. The resistive field plate extends toward the second electrode while surrounding a periphery of the first electrode in a scroll shape. A resistance value of a total resistance of the resistive field plate is in a range between 90 k? and 90 M?.Type: ApplicationFiled: November 14, 2011Publication date: May 17, 2012Applicant: DENSO CORPORATIONInventors: Norihito TOKURA, Takao Yamamoto, Hisato Kato, Kouji Senda, Akio Nakagawa
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Publication number: 20120061726Abstract: A N-channel lateral insulated-gate bipolar transistor includes a semiconductor substrate, a drift layer, a collector region, a channel layer, an emitter region, a gate insulation film, a gate electrode, a collector electrode, an emitter electrode. The collector region includes a high impurity concentration region having a high impurity concentration and a low impurity concentration region having a lower impurity concentration than the high impurity concentration region. The collector electrode is in ohmic contact with the high impurity concentration region and in schottky contact with the low impurity concentration region.Type: ApplicationFiled: September 7, 2011Publication date: March 15, 2012Applicant: DENSO CORPORATIONInventors: Norihito TOKURA, Shigeki Takahashi, Youichi Ashida, Akio Nakagawa
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Publication number: 20120047418Abstract: An information processing apparatus comprising: a reception unit adapted to receive a packet containing first data to be stored in a storage unit, a first address indicating an address of second data held in the storage unit, and a second address indicating an address at which the first data is to be written in the storage unit; an access unit adapted to read out the second data from the storage unit based on the first address, and write the first data in the storage unit based on the second address; and a transmission unit adapted to replace the first data of the packet received by the reception unit with the second data read out by the access unit, and transmit the packet.Type: ApplicationFiled: July 1, 2011Publication date: February 23, 2012Applicant: CANON KABUSHIKI KAISHAInventors: Akio Nakagawa, Hisashi Ishikawa
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Publication number: 20120032313Abstract: A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.Type: ApplicationFiled: August 3, 2011Publication date: February 9, 2012Applicant: DENSO CORPORATIONInventors: Takao YAMAMOTO, Norihito Tokura, Hisato Kato, Akio Nakagawa