Abstract: Clocked low power logic circuitry with static inputs and outputs is adiabatically operated. A variety of logical functions is achieved without complex circuitry or unusually configured devices. This logic circuitry can be configured to perform a variety of logical and storage functions.

Abstract: An energy efficient logic gate circuit design that provides a substantially constant load to a clock source regardless of logic signal inputs to, or outputs from, the gate. The gate provides two complementary outputs and utilizes cross-coupled transistors to ensure that the outputs remain valid (complementary) after the logic inputs become invalid. Two blocks, each having a node coupling to the clock source and performing complementary logic functions, in combination with diodes for recharging the outputs of the gate, present the constant load to the clock source.

Abstract: A novel family of adiabatic dynamic logic gates can have power*delay products at least an order of magnitude or more below that which was possible in previous families of logic gates. No complex circuitry or unusually configured devices are needed to implement this logic family. In particular, this logic family requires fewer devices and less area per logic gate as compared with ordinary CMOS logic circuitry. This is unlike previous reversible logic proposals which required large numbers of transistors per gate. This logic circuitry can operate from very low supply voltages and need not be optimized for a particular voltage. This logic does not suffer from crowbar currents usually found in prior circuitry such as CMOS logic. Logic levels are regenerated at nearly every stage unlike some previous schemes which reduce energy dissipation only by sacrificing logic levels.

Abstract: A novel family of adiabatic dynamic logic gates can have power*delay products at least an order of magnitude or more below that which was possible in previous families of logic gates. No complex circuitry or unusually configured devices are needed to implement this logic family. In particular, this logic family requires fewer devices and less area per logic gate as compared with ordinary CMOS logic circuitry. This is unlike previous reversible logic proposals which required large numbers of transistors per gate. This logic circuitry can operate from very low supply voltages and need not be optimized for a particular voltage. This logic does not suffer from crowbar currents usually found in prior circuitry such as CMOS logic. Logic levels are regenerated at nearly every stage unlike some previous schemes which reduce energy dissipation only by sacrificing logic levels.

Abstract: CMOS logic circuitry powered by the clock signals wherein the addition of strategically placed diodes enables the circuits to behave in an adiabatic-like fashion.

Abstract: Maximum operating speed is achieved in an array of memory cells by performing both read and write operations within a single memory cycle. As outgoing data are read from the memory cells, incoming data are stored immediately in those cells. Reduced power consumption is achieved in such memories by preventing the occurrance of a write operation if the value of a bit to be written to a memory cell is the same as the value of the bit currently stored in that memory cell. More particularly, the result of a read operation on a particular memory cell is compared with the data value to be written to that cell to determine whether a subsequent write operation is required. If the value in the cell equals the value to be written, the write operation is not performed.

Abstract: Reduced manufacturing costs and wafer size, lower power consumption, and increased operating speed are achieved in memory circuits by providing a novel sense amplifier design that is most sensitive to voltages variations around the source voltage (V.sub.dd). The sense amplifier includes two inverters that are regeneratively cross-coupled through a circuit that is controlled by a system clock. The inverters are powered from the bit lines that couple the sense amplifier to a memory cell. Novel applications of the sense amplifier in memory circuits also are described.

Abstract: A memory is partitioned into rows and columns of memory blocks comprised of latches, sense amplifiers, and logic circuitry that form independent pipelines through which flow a) input addresses for memory access requests and b) data to be written into a specific memory cell within a memory block. The memory allows multiple data access requests in consecutive clock cycles to be pipelined in the rows and columns of memory blocks such that the memory clock speed is equal to the clock speed of a single memory block, independently of the memory size.

Abstract: Maximum operating speed is achieved in an array of memory cells by performing both read and write operations within a single memory cycle. As outgoing data are read from the memory cells, incoming data are stored immediately in those cells. Once data are read from the memory cells, a latch signal is generated to trigger latching of the read data for output to a data bus. The same latch signal that is used to latch the read data initiates the writing of new data to the memory cells. Use of a single latch signal in this manner ensures that new data are not written to the memory cells until the existing data has been read from those cells.