Patents by Inventor Alexander Reznicek

Alexander Reznicek has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RACETRACK MEMORY FOR ARTIFICIAL INTELLIGENCE APPLICATIONS
    Publication number: 20230116251
    Abstract: A semiconductor structure is provided. The semiconductor device includes a magnetic layer located between a first electrode and a second electrode formed on a substrate. The semiconductor device further includes a first write element electrically coupled to the magnetic layer adjacent to the first electrode. The semiconductor device also includes a second write element electrically coupled to the magnetic layer adjacent to the second electrode. The semiconductor device additionally includes a plurality of read elements electrically coupled to the magnetic layer located between the first write element and the second write element.
    Type: Application
    Filed: September 29, 2021
    Publication date: April 13, 2023
    Inventors: Heng Wu, Alexander Reznicek, Ruilong Xie, Julien Frougier, Chen Zhang
  • STACKED COMPLEMENTARY FIELD EFFECT TRANSISTORS
    Publication number: 20230103999
    Abstract: A CFET (complementary field effect transistor) structure including a first transistor disposed above a second transistor, a first source/drain region of the first transistor disposed above a second source/drain region of the second transistor, a first source/drain contact for the first source/drain region, and a second source drain contact for the second source drain region. The first source/drain contact is isolated from the second source/drain contact by an L-shaped isolation element including vertical and horizontal isolation elements.
    Type: Application
    Filed: October 5, 2021
    Publication date: April 6, 2023
    Inventors: HUIMEI ZHOU, Alexander Reznicek, MIAOMIAO WANG, Ruilong Xie
  • SECURE CHIP IDENTIFICATION USING RANDOM THRESHOLD VOLTAGE VARIATION IN A FIELD EFFECT TRANSISTOR STRUCTURE AS A PHYSICALLY UNCLONABLE FUNCTION
    Publication number: 20230109345
    Abstract: A semiconductor structure may include one or more metal gates, one or more channels below the one or more metal gates, a gate dielectric layer separating the one or more metal gates from the one or more channels, and a high-k material embedded in the gate dielectric layer. Both the high-k material and the gate dielectric layer may be in direct contact with the one or more channels. The high-k material may provide threshold voltage variation in the one or more metal gates. The high-k material is a first high-k material or a second high-k material. The semiconductor structure may only include the first high-k material embedded in the gate dielectric layer. The semiconductor structure may only include the second high-k material embedded in the gate dielectric layer. The semiconductor structure may include both the first high-k material and the second high-k material embedded in the gate dielectric layer.
    Type: Application
    Filed: December 6, 2022
    Publication date: April 6, 2023
    Inventors: Clint Jason Oteri, Alexander Reznicek, Bahman Hekmatshoartabari, Jingyun Zhang, Ruilong Xie
  • ARTIFICIAL INTELLIGENCE (AI) DEVICES WITH IMPROVED THERMAL STABILITY AND SCALING BEHAVIOR
    Publication number: 20230105007
    Abstract: A phase change memory semiconductor structure includes a substrate; a landing pad located in the substrate; a dielectric located outwardly of the substrate; a heater element located in the substrate outward of the landing pad; a stack including an inner undoped chalcogenide layer outward of the dielectric, a doped chalcogenide layer outward of the inner undoped chalcogenide layer, and an outer undoped chalcogenide layer outward of the doped chalcogenide layer; and at least one lateral conductive metal layer associated with the stack.
    Type: Application
    Filed: October 4, 2021
    Publication date: April 6, 2023
    Inventors: Injo Ok, Alexander Reznicek, Youngseok Kim, Soon-Cheon Seo
  • RESISTIVE SWITCHING DEVICE HAVING A PROTECTIVE ELECTRODE RING
    Publication number: 20230109660
    Abstract: Embodiments of the invention are directed to a structure that includes a resistive switching device (RSD). The RSD includes a first terminal having an outer sidewall surface; a second terminal; an active region having a switchable conduction state; and a first protective layer on the outer sidewall surface of the first terminal.
    Type: Application
    Filed: September 24, 2021
    Publication date: April 6, 2023
    Inventors: Takashi Ando, Ruilong Xie, Alexander Reznicek, Pouya Hashemi
  • Wraparound contact to a buried power rail
    Patent number: 11621332
    Abstract: An approach to form a semiconductor structure with a buried power rail. The semiconductor structure includes a buried power rail in a semiconductor substrate where a buried contact contacts to a first portion of a top surface of the buried power rail to a source/drain of a semiconductor device. Additionally, the semiconductor structure includes a first portion of a top surface of the buried contact that is below a top surface of the source/drain of the semiconductor device and a portion of a bottom surface of the buried contact that is in a cavity formed in the source/drain of the semiconductor device.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: April 4, 2023
    Assignee: International Business Machines Corporation
    Inventors: Ruilong Xie, Veeraraghavan S. Basker, Alexander Reznicek, Junli Wang
  • Stackable symmetrical operation memory bit cell structure with bidirectional selectors
    Patent number: 11621297
    Abstract: A method of forming an electrical device that includes forming an amorphous semiconductor material on a metal surface of a memory device, in which the memory device is vertically stacked atop a first transistor. The amorphous semiconductor material is annealed with a laser anneal having a nanosecond duration to convert the amorphous semiconductor material into a crystalline semiconductor material. A second transistor is formed from the semiconductor material. The second transistor vertically stacked on the memory device.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 4, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alexander Reznicek, Bahman Hekmatshoartabari, Oleg Gluschenkov, Yasir Sulehria
  • BACKSIDE POWER RAILS
    Publication number: 20230100113
    Abstract: Integrated chips and methods of forming the same include forming a stack of layers, including a device stack above a first sacrificial layer, above a substrate. The first sacrificial layer is replaced with a first etch stop layer. The substrate is removed, exposing a substrate-side of the stack of layers. The substrate-side of the stack of layers is etched to form a trench, stopping on the first etch stop layer. A conductive line is formed in the trench.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 30, 2023
    Inventors: Ruilong Xie, Stuart Sieg, Somnath Ghosh, Kisik Choi, Rishikesh Krishnan, Alexander Reznicek
  • NANOSHEET DEVICE WITH TRI-LAYER BOTTOM DIELECTRIC ISOLATION
    Publication number: 20230099214
    Abstract: A nanosheet device includes a bottom dielectric isolation formed by a first portion of a high-k dielectric layer above a semiconductor substrate, a spacer material above the first portion of the high-k dielectric layer and a second portion of the high-k dielectric layer above the spacer material. A sequence of semiconductor channel layers are stacked perpendicularly to the semiconductor substrate above the bottom dielectric isolation and are separated by and vertically aligned with a metal gate stack. Source/drain regions extend laterally from opposite ends of the semiconductor channel layers with a bottom surface of the source/drain regions being in direct contact with the bottom dielectric isolation for electrically isolating the source/drain regions from the semiconductor substrate.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Xin Miao, Jingyun Zhang, Alexander Reznicek, Choonghyun Lee
  • LOW PROGRAM VOLTAGE FLASH MEMORY CELLS WITH EMBEDDED HEATER IN THE CONTROL GATE
    Publication number: 20230097904
    Abstract: A method of manufacturing a low program voltage flash memory cell with an embedded heater in the control gate creates, on a common device substrate, a conventional flash memory cell in a conventional flash memory area (CFMA), and a neuromorphic computing memory cell in a neuromorphic computing memory area (NCMA). The method comprises providing a flash memory stack in both the CFMA and the NCMA, depositing a heater on top of the flash memory stack in the NCMA without depositing a heater on top of the flash memory stack in the CFMA.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 30, 2023
    Inventors: Takashi Ando, Nanbo Gong, Bahman Hekmatshoartabari, Alexander Reznicek
  • USING DIFFERENT WORK-FUNCTIONS TO REDUCE GATE-INDUCED DRAIN LEAKAGE CURRENT IN STACKED NANOSHEET TRANSISTORS
    Publication number: 20230099254
    Abstract: Embodiments of the invention are directed to a transistor device that includes a channel stack having stacked, spaced-apart, channel layers. A first source or drain (S/D) region is communicatively coupled to the channel stack. A tunnel extends through the channel stack, wherein the tunnel includes a central region and a first set of end regions. The first set of end regions is positioned closer to the first S/D region than the central region is to the first S/D region. A first type of work-function metal (WFM) is formed in the first set of end regions, the first WFM having a first work-function (WF). A second type of WFM is formed in the central region, the second type of WFM having a second WF, wherein the first WF is different than the second WF.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Takashi Ando, Ruilong Xie, Pouya Hashemi, Alexander Reznicek
  • TOP EPITAXIAL LAYER AND CONTACT FOR VTFET
    Publication number: 20230086681
    Abstract: A semiconductor device includes first and second vertical transport field-effect transistor (VTFET) devices. Each of the first and second VTFET devices includes a bottom epitaxial layer, a plurality of channel fins formed on the bottom epitaxial layer, a first interlayer dielectric (ILD) layer formed between the channel fins, a high-? metal gate formed between the channel fins and the first ILD layer, a top epitaxial layer formed discretely on each of the channel fins, and a trench epitaxial layer formed continuously across the top epitaxial layer, a portion of the first ILD layer also being formed between the first and second VTFET device. The semiconductor device also includes a second ILD layer formed on the portion of the first ILD layer that is between the first and second VTFET devices, the second ILD layer separating the top epitaxial layers of the first and second VTFET devices.
    Type: Application
    Filed: September 23, 2021
    Publication date: March 23, 2023
    Inventors: RUILONG XIE, CHRISTOPHER J WASKIEWICZ, ALEXANDER REZNICEK, SU CHEN FAN, HENG WU
  • BOTTOM JUNCTION AND CONTACT AREA STRUCTURES FOR VERTICAL TRANSPORT FIELD-EFFECT TRANSISTORS
    Publication number: 20230091229
    Abstract: A semiconductor structure comprises at least one vertical fin, an epitaxial layer adjacent a bottom portion of the at least one vertical fin, wherein the epitaxial layer comprises a plurality of different heights, and a contact structure disposed on the epitaxial layer. The contact structure is disposed on respective surfaces of the epitaxial layer at the plurality of different heights. The epitaxial layer comprises a bottom source/drain region of at least one vertical transport field-effect transistor.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Tao Li, Ruilong Xie, Yann Mignot, Tsung-Sheng Kang, Alexander Reznicek
  • STACKED SPIN-ORBIT TORQUE MAGNETORESISTIVE RANDOM ACCESS MEMORY
    Publication number: 20230089984
    Abstract: A semiconductor structure includes a bottom MTJ stack with a bottom fixed layer, a bottom barrier layer, and a bottom free layer. The semiconductor structure also includes a top MTJ stack with a top fixed layer, a top barrier layer, and a top free layer. Additionally, the semiconductor structure also includes a spin-Hall effect (SHE) rail with a dielectric, a top heavy metal layer, and a bottom heavy metal layer.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 23, 2023
    Inventors: Heng Wu, Alexander Reznicek, Bahman Hekmatshoartabari, Ruilong Xie
  • BURIED LOCAL INTERCONNECT BETWEEN COMPLEMENTARY FIELD-EFFECT TRANSISTOR CELLS
    Publication number: 20230089185
    Abstract: An integrated circuit component includes a first layer including first and second areas of epitaxy material. The first layer has a first polarity. The component further includes a second layer including third and fourth areas of epitaxy material. The second layer has a second polarity that is different than the first polarity. The third area is arranged at least partially above the first area, and the fourth area is arranged at least partially above the second area. The integrated circuit component further includes an interconnect in direct contact with one of the first area and the third area and in direct contact with one of the second area and the fourth area. The interconnect has a top surface that does not extend substantially above an uppermost surface of the second layer.
    Type: Application
    Filed: September 17, 2021
    Publication date: March 23, 2023
    Inventors: Ruilong Xie, REINALDO VEGA, Alexander Reznicek, Kangguo Cheng
  • HYBRID STACKED FIELD EFFECT TRANSISTORS
    Publication number: 20230085628
    Abstract: A hybrid stacked semiconductor device includes a nanosheet stack on a substrate and an all-around gate. The nanosheet stack includes a first stack portion and a second stack portion. The first stack portion includes first channels. The second stack portion is stacked on the first stack portion, and includes second channels. The all-around gate includes a first gate portion that wraps around the first channels and a second gate portion that wraps around the second channels. A first gate extension contacts the first gate portion and the second gate extension contacts the second gate portion. At least one gate contact contacts the first gate extension to establish conductivity with the first gate portion and contacts the second gate extension to establish conductivity with the second gate portion.
    Type: Application
    Filed: September 22, 2021
    Publication date: March 23, 2023
    Inventors: Ruilong Xie, Bahman Hekmatshoartabari, Alexander Reznicek, Heng Wu
  • PHASE-CHANGE MEMORY WITH EMBEDDED AIR GAP
    Publication number: 20230093604
    Abstract: A phase-change memory cell comprises a heater element. The heater element comprises a first resistive material, a conductive material, and a second resistive material. The first resistive material, second resistive material, and conductive material together form a well. The phase-change memory cell also comprises a deposition of dielectric material plugs the well, and an insulator gap within the well that is enclosed by the first resistive material, the conductive material, and the second resistive material.
    Type: Application
    Filed: September 21, 2021
    Publication date: March 23, 2023
    Inventors: Injo Ok, Soon-Cheon Seo, Alexander Reznicek, Youngseok Kim
  • INTEGRATED NANOSHEET FIELD EFFECT TRANSISTORS AND FLOATING GATE MEMORY CELLS
    Publication number: 20230085033
    Abstract: A semiconductor device including a nanosheet field effect transistor (FET) comprising a thin gate oxide layer and a floating gate memory cell comprising a tunneling oxide, a floating gate, and a blocking oxide layer over a fin FET device. The device fabricated by forming a nanosheet stack and fin structures, forming tunneling oxide and floating gate layers over the nanosheet stack and fin structures, forming dummy gate structures over the nanosheet stack and fin structures, removing the dummy gate structures, forming a blocking oxide layer over the floating gate, and forming replacement metal gates.
    Type: Application
    Filed: September 13, 2021
    Publication date: March 16, 2023
    Inventors: Ruilong Xie, Julien Frougier, Veeraraghavan S. Basker, Alexander Reznicek
  • Self-Aligned Via to Metal Line for Interconnect
    Publication number: 20230077878
    Abstract: Interconnect structures having top vias self-aligned to metal line ends and techniques for formation thereof are provided. In one aspect, an interconnect structure includes: at least one metal line disposed on a substrate; at least one top via over the at least one metal line, wherein the at least one top via is aligned with an end of the at least one metal line, and wherein a sidewall of the at least one top via is curved. A dielectric fill material can be disposed adjacent to the at least one top via having sidewalls that are also curved. A method of fabricating an interconnect structure is also provided.
    Type: Application
    Filed: September 15, 2021
    Publication date: March 16, 2023
    Inventors: Tao Li, Ruilong Xie, Tsung-Sheng Kang, Alexander Reznicek
  • Dual resistive random-access memory with two transistors
    Patent number: 11605673
    Abstract: An approach to forming a semiconductor structure is provided. The semiconductor structure includes two adjacent fins on a substrate. A gate stack is on each of the two adjacent fins. The semiconductor structure includes a first source/drain on a first end of each fin of the two adjacent fins and a second source/drain on a second end of each fin of the two adjacent fins. The semiconductor structure includes a switching layer on at least the first source/drain on the first end of each fin of the two adjacent fins and a top electrode on the switching layer. A metal material over the top electrode in the semiconductor structure.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: March 14, 2023
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Tsung-Sheng Kang, Takashi Ando, Bahman Hekmatshoartabari