Abstract: A method of manufacturing a magnetic tunnel junction device is provided. The method includes forming an MTJ stack including a reference layer, a tunnel barrier layer formed on the reference layer, a free layer formed on the barrier layer, and a cap layer formed on the free layer. The method also includes performing ion beam etching (IBE) through each layer of the MTJ stack to form at least one MTJ pillar. The method also includes forming an isolation layer on sidewalls of at least the tunnel barrier layer, the isolation layer comprising a same material as that of the tunnel barrier layer. A combined width of the isolation layer and the tunnel barrier layer is equal to or greater than a width of at least one of the reference layer and the free layer.

Abstract: A semiconductor device including at least one nanosheet and epitaxial source and drain regions are present on opposing ends of the at least one nanosheet. A gate structure is present on a channel of the at least one nanosheet. The gate structure includes a first work function metal gate portion present at a junction portion of the source and drain regions that interfaces with the channel portion of the at least one nanosheet, and a second work function metal gate portion present on a central portion of the channel of the at least one nanosheet. The amount of metal containing nitride in the second work function metal gate portion is greater than an amount of metal containing nitride in the first work function metal gate portion. The device further includes a rotated T-shaped dielectric spacer present between the gate structure and the epitaxial source and drain regions.

Abstract: A semiconductor device structure comprises at least one semiconductor fin for a vertical transport field effect transistor, a bottom source/drain layer, and an insulating layer underlying the bottom source/drain layer. A method of forming the structure comprises forming a sacrificial layer within a lower portion of a source/drain region for a vertical transport field effect transistor structure. The sacrificial layer being formed adjacent to at least one semiconductor fin and in contact with a substrate. A source/drain layer is formed within an upper portion of the source/drain region above the sacrificial layer. The sacrificial layer is removed thereby forming a cavity between the substrate and the source/drain layer. An insulating layer is formed within the cavity.

Abstract: A method of manufacturing a vertical transistor device comprises forming a bottom source region on a semiconductor substrate, forming a channel region extending vertically from the bottom source region, forming a top drain region on an upper portion of the channel region, forming a first gate region having a first gate length around the channel region, and forming a second gate region over the first gate region and around the channel region, wherein the second gate region has a second gate length different from the first gate length, and wherein at least one dielectric layer is positioned between the first and second gate regions.

Abstract: A method is presented for constructing a nanosheet transistor. The method includes forming a nanosheet stack including alternating layers of a first material and a second material over a substrate, forming a dummy gate over the nanosheet stack, forming sacrificial spacers adjacent the dummy gate, and selectively etching the alternating layers of the first material to define gaps between the alternating layers of the second material. The method further includes filling the gaps with inner spacers, epitaxially growing source/drain regions adjacent the nanosheet stack, selectively removing the sacrificial spacers and the inner spacers to define cavities, and filling the cavities with a spacer material to define first airgaps adjacent the dummy gate and second airgaps adjacent the etched alternating layers of the first material.

Abstract: A memory device is provided that includes at least one MTJ pillar which can have a ternary program state as compared to a binary program state in a conventional device. The MTJ pillar contains a lower MTJ structure that includes at least a first magnetic reference material, a first tunnel barrier and a first magnetic free layer material, and an upper MTJ structure that includes at least a second magnetic reference material, a second tunnel barrier and a second magnetic free layer material; the upper MTJ structure is stacked atop the lower MTJ structure. The first and second magnetic free layer materials have different designs and/or compositions resulting in different switching voltages.

Abstract: A circuit may include a memory cell. The memory cell may include a first memory element, a second memory element, a first transistor, and a second transistor. The first memory element may be connected to a bit line. The second memory element may be connected to a select line. The first transistor may be connected to a first word line. The second transistor may be connected to a second word line. The first memory element may be programmed by applying a first write voltage to the bit line, applying a second write voltage to the second word line, applying a first intermediate voltage to the select line, and applying a second intermediate voltage to the first word line. The select line may be connected to a high impedance. The first write voltage may be a positive supply voltage, the second write voltage may be a negative supply voltage.

Abstract: An integrated circuit (IC) is provided that includes a plurality of physical unclonable function (PUF) structures located in a PUF area. Each PUF structure of the plurality of PUF structures includes at least a PUF top electrically conductive structure containing random sidewall voids and random line openings which can provide an encrypted security code to the IC. The IC further includes a plurality of memory structures located in a memory area that is located laterally adjacent to the PUF area. Each memory structure of the plurality of memory structures includes a memory element sandwiched between a bottom electrically conductive structure and a top electrically conductive structure. The top electrically conductive structures are devoid of sidewall voids and line openings.

Abstract: A ring-shaped heater, system, and method to gradually change the conductance of the phase change memory through a concentric ring-shaped heater. The system may include a phase change memory. The phase change memory may include a bottom electrode. The phase change memory may also include a ring-shaped heater patterned on top of the bottom electrode, the ring-shaped heater including: a plurality of concentric conductive heating layers, and a plurality of insulator spacers, where each insulator spacer separates each conductive heating layer. The phase change memory may also include a phase change material proximately connected to the ring-shaped heater. The phase change memory may also include a top electrode proximately connected to the phase change material.

Abstract: A phase change memory, system, and method for gradually changing the conductance and resistance of the phase change memory while preventing resistance drift. The phase change memory may include a phase change material. The phase change memory may also include a bottom electrode. The phase change memory may also include a heater core proximately connected to the bottom electrode. The phase change memory may also include a set of conductive rings surrounding the heater core, where the set of conductive rings comprises one or more conductive rings, and where the set of conductive rings are proximately connected to the phase change material. The phase change memory may also include a set of spacers, where a spacer, from the set of spacers, separates a portion of a conductive ring, from the set of conductive rings, from the heater core.

Abstract: A stacked semiconductor device comprising a lower source/drain epi located on top of a bottom dielectric layer. An isolation layer located on top of the lower source/drain epi and an upper source/drain epi located on top of the isolation layer. A lower electrical contact that is connected to the lower source/drain epi, wherein the lower electrical contact is in direct contact with multiple side surfaces of the lower source/drain epi.

Abstract: A method for fabricating stacked resistive memory with individual switch control is provided. The method includes forming a first random access memory (ReRAM) device. The method further includes forming a second ReRAM device in a stacked nanosheet configuration on the first ReRAM device. The method also includes forming separate gate contacts for the first ReRAM device and the second ReRAM device.

Abstract: A semiconductor structure for triggering asymmetric threshold voltage along a channel of a vertical transport field effect transistor (VTFET) is provided. The semiconductor structure includes a first set of fins including a SiGe layer and a first material layer formed on the SiGe layer, a second set of fins including the SiGe layer and a second material layer formed on the SiGe layer, a first high-? metal gate disposed over the first set of fins, and a second high-? metal gate disposed over the second set of fins. An asymmetric threshold voltage is present along the channel of the VTFET in a region defined at a bottom of the first and second set of fins, and a Ge content of the second material layer is higher than a Ge content of the SiGe layer.

Abstract: A semiconductor structure may include a metal line, a via above and in electrical contact with the metal lines, and a dielectric layer positioned along a top surface of the metal lines. A top surface of the dielectric layer may be below the dome shaped tip of the via. A top portion of the via may include a dome shaped tip. The semiconductor structure may include a liner positioned along the top surface of the dielectric layer and a top surface of the dome shaped tip of the via. The liner may be made of tantalum nitride or titanium nitride. The dielectric layer may be made of a low-k material. The metal line and the via may be made of ruthenium. The metal line may be made of molybdenum.

Abstract: A semiconductor structure may include a buried power rail under a bottom source drain of a vertical transistor and a dielectric bi-layer under the bottom source drain. The dielectric bi-layer may be between the buried power rail and the bottom source drain. The semiconductor structure may include a silicon germanium bi-layer under the bottom source drain, the silicon germanium bi-layer may be adjacent to the buried power rail. The semiconductor structure may include a buried power rail contact. The buried power rail contact may connect the bottom source drain to the buried power rail. The dielectric bi-layer may include a first dielectric layer and a dielectric liner. The first dielectric layer may be in direct contact with the bottom source drain. The dielectric liner may surround the buried power rail. The silicon germanium bi-layer may include a first semiconductor layer and a second semiconductor layer below the first semiconductor layer.

Abstract: A tilted nanowire structure is provided which has an increased gate length as compared with a horizontally oriented semiconductor nanowire at the same pitch. Such a structure avoids complexity required for vertical transistors and can be fabricated on a bulk semiconductor substrate without significantly changing/modifying standard transistor fabrication processing.

Abstract: A method of manufacturing a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of first type sacrificial layers and active semiconductor layers. The method includes forming the first type sacrificial layer on sidewalls of the nanosheet stacks, then forming a dielectric pillar between the sidewall portions of the first type sacrificial layers of adjacent nanosheet stacks, and then removing the first type sacrificial layer. The method also includes forming a PWFM layer in spaces formed by the removal of the first type sacrificial layer for a first one of the nanosheet stacks, and includes forming a NWFM layer in spaces formed by the removal of the first type sacrificial layer for an adjacent second one of the nanosheet stacks.

Abstract: An embodiment of the invention may include a method of forming and a resulting multiply-and-accumulate device. The device may include a capacitor in a second region. The capacitor comprises a dielectric located between a first metal contact and a second metal contact. The device may include a stacked nanosheet device in the first region from the nanosheet. The stacked nanosheet device may include a top transistor and a bottom transistor in contact with the first metal contact. The device may include a nanosheet device in the third region, wherein a source/drain of a transistor of the nanosheet device is in contact with the first metal contact.

Abstract: Semiconductor devices include a stack of vertically arranged channel layers. A gate stack is formed above, between, and around the vertically arranged channel layers. Source and drain regions and source and drain conductive contacts are formed. Inner spacers are formed between the vertically arranged channel layers, each having an inner air gap and a recessed layer formed from a first dielectric material. Outer spacers are formed between the gate stack and the source and drain conductive contacts, each having a second dielectric material that is pinched off to form an outer air gap.

Abstract: Semiconductor devices and method of forming the same include recessing sacrificial layers relative to the channel layers, in a stack of vertically aligned, alternating sacrificial layers and channel layers, to form first recesses. A dual-layer dielectric is deposited that includes a first dielectric material formed conformally on surfaces of the recesses and a second dielectric material filling a remainder of the first recesses. The first dielectric material is recessed relative to the second dielectric material to form second recesses. Additional second dielectric material is deposited to fill the second recesses. The second dielectric material and the additional second dielectric material is etched away to create air gaps.