Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

Abstract: Systems and methods for in-band reset and wake up on a differential audio bus are disclosed. In particular, after entering a low-power mode, a master device opens a drain on a transistor driving the differential audio bus. When a slave device needs the bus to wake, the slave device may transition the state of the bus. On detecting the transition of the bus, the master device may reassert control of the state of the bus and hold the bus in this new state until ready to issue a synchronization sequence. Likewise, an additional aspect of the present disclosure provides a distinctive sequence of holding the bus at a predefined state for an extended duration interrupted by a relatively brief reversal of the state that triggers a reset of all slave devices on the audio bus.

Abstract: Aspects disclosed in the detailed description include scheduled universal serial bus (USB) low-power operations. In this regard, in one aspect, a USB host controller determines a low-power operation schedule for a USB client device. The low-power operation schedule comprises one or more scheduled low-power operation periods, each corresponding to a respective entry time and a respective exit time. The USB host controller communicates the low-power operation schedule to the USB client device using one or more USB standard packets. By scheduling the one or more scheduled low-power operation periods with respective entry and exit times, the USB host controller or the USB client controller is able to start and end the one or more scheduled low-power operation periods without incurring additional signaling, thus improving efficiency of the USB low-power operation. Further, by communicating the low-power operation schedule using USB standard packets, it is possible to preserve compatibility with USB standards.

Abstract: A system for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems, while maintaining both lower level physical layer (PHY) pin requirements and upper layer functionality being capable of both differential and single-ended signaling modes optimized for power savings. An apparatus includes an integrated circuit (IC) adapted to be connected to a Peripheral Component Interconnect (PCI) Express (PCIe) bus. The IC includes a control block selects between differential and single-ended signaling for the PCIe bus. The single-ended signaling is transmitted through existing pins of the IC that are coupled to the PCIe bus for differential signaling when single-ended signaling is selected for the PCIe bus.

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. An apparatus has a bus including a first lane and a second lane, a plurality of devices coupled to the bus and, in a first mode of operation, the plurality of devices is configured to exchange data in a signal transmitted on the first lane in accordance with timing provided by a clock signal transmitted on the second lane. The apparatus may include one or more additional lanes connecting two or more devices in the plurality of devices, the two or more devices being configured to use the first lane and at least one of the additional lanes for data transmissions in a second mode of operation.

Abstract: Alternate acknowledgment (ACK) signals in a coalescing Transmission Control Protocol/Internet Protocol (TCP/IP) system are disclosed. In one aspect, a network interface card (NIC) examines packet payloads, and the NIC generates an ACK signal for a sending server before sending a coalesced packet to an internal processor. Further, the NIC may examine incoming packets and send an ACK signal to the internal processor for ACK signals that are received from the sending server before sending the coalesced packet to the internal processor. By extracting and sending the ACK signals before sending the corresponding payloads in the coalesced packet, latency that would otherwise be incurred waiting for the ACK signal is eliminated. Elimination of such latency may improve network performance and may provide power savings.

Abstract: System, methods and apparatus are described that can improve available bandwidth on a SoundWire bus without increasing the number of pins used by the SoundWire bus. A method performed at a master device coupled to a SoundWire bus includes providing a clock signal by a first master device over a clock line of a SoundWire bus to a first slave device and a second slave device coupled to the SoundWire bus, transmitting first control information from the first master device to the first slave device over a first data line of the SoundWire bus, and transmitting second control information from the first master device to the second slave device over a second data line of the SoundWire bus. The first control information may be different from the second control information and is transmitted concurrently with the second control information.

Abstract: Communicating transaction-specific attributes in a peripheral component interconnect express (PCIe) system is disclosed. A PCIe system includes a host system and at least one PCIe endpoint. The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. In this regard, in one aspect, the PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. In another aspect, a PCIe root complex (RC) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.

Abstract: SoundWire-based embedded debugging in an electronic system is provided. In this regard, in one aspect, a SoundWire slave circuit receives a SoundWire data input signal over a SoundWire bus including two physical wires. The SoundWire data input signal includes a plurality of debug configuration bits in assigned SoundWire bitslots. The SoundWire slave circuit generates a plurality debug input bits required for debugging the SoundWire slave circuit based on the debug configuration bits received in the assigned SoundWire bitslots. In another aspect, the SoundWire slave circuit returns a SoundWire data output signal, which includes a debug output bit in an assigned SoundWire bitslot, over the SoundWire bus. By receiving debugging configurations and returning debugging results over the SoundWire bus, it is possible to debug the SoundWire slave circuit with a reduced number of physical pins, thus helping to reduce the overall pin count and footprint of the electronic device.

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

Abstract: Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.

Abstract: System, methods, and apparatuses are described that facilitate a first device to transmit/retransmit a message to a second device. The first device transmits a first message to the second device. The first device then receives a second message and identifies a bit of the second message indicating an originator of the second message. If the bit indicates the first device as the originator of the second message, then the second message is an echo of the first message. Reception of the echo indicates that the second device is in a sleep state. Accordingly, the first device waits for the second device to wake and retransmits the first message to the second device to ensure that any packets lost during the original transmission of the first message (when the second device was asleep) are now retransmitted while the second device is known to be awake.

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

Abstract: Systems and methods for handling silence in audio streams are disclosed. In one aspect, a transmitter detects a halt in an audio stream. After detection of the halt in the audio stream, the transmitter embeds a silence signal into the audio stream and transmits the silence signal to associated receivers. The associated receivers may respond to the embedded silence signal by “playing” silence or by using the silence signal to activate a silence protocol. In either event, the associated receivers do not receive the original audio halt and do not produce an unwanted audio artifact.

Abstract: Methods of operation and computer program products for enabling a user to employ a single discrete navigation gesture to select and launch a mobile device destination. The mobile device destination can be a child mobile device destination pointed to by a parent mobile device destination. The mobile device destination can be a user selected mobile device destination from a library of mobile device destinations too long to be depicted simultaneously on a display screen. One embodiment requires a user to draw an additional segment of a single discrete navigation gesture to change one or more instantaneously depicted mobile device destination icons. Another embodiment requires a user to maintain user contact on a navigation item to change one or more instantaneously depicted mobile device destination icons.

Abstract: SoundWire-based embedded debugging in an electronic system is provided. In this regard, in one aspect, a SoundWire slave circuit receives a SoundWire data input signal over a SoundWire bus including two physical wires. The SoundWire data input signal includes a plurality of debug configuration bits in assigned SoundWire bitslots. The SoundWire slave circuit generates a plurality debug input bits required for debugging the SoundWire slave circuit based on the debug configuration bits received in the assigned SoundWire bitslots. In another aspect, the SoundWire slave circuit returns a SoundWire data output signal, which includes a debug output bit in an assigned SoundWire bitslot, over the SoundWire bus. By receiving debugging configurations and returning debugging results over the SoundWire bus, it is possible to debug the SoundWire slave circuit with a reduced number of physical pins, thus helping to reduce the overall pin count and footprint of the electronic device.

Abstract: A virtualized Internet Protocol (IP) packet processing system is provided. In this regard, in one aspect, a computing circuit for processing IP packets is shared among a plurality of virtual clients. The computing circuit includes a plurality of hardware functional blocks each configured to perform a predefined IP packet processing function. In another aspect, a virtual channel is created for each of the virtual clients and assigned with one or more of the hardware functional blocks. In this regard, IP packets associated with each of the virtual clients may be processed by respective assigned hardware functional blocks based on a specified processing sequence. By sharing the computing circuit among the virtual clients and assigning respective hardware functional blocks to each virtual client, it is possible to optimize processing efficiency of the computing circuit, thus improving throughput, latency, and power consumption of the virtualized IP packet processing system.

Abstract: Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.