Abstract: Described is an apparatus which comprises: a driver comprising a push-pull transmitter; a first circuitry to sense variation in a power supply; and a second circuitry coupled to the first circuitry and to the driver, the second circuitry to generate a code according to an output of the first circuitry, wherein the code is provided to the driver to adjust a performance parameter of the driver.

Abstract: In one embodiment, an apparatus includes a clock control circuit to generate a clock signal for communication on an interconnect. The clock control circuit may be configured to receive an indication of a next device of a plurality of devices to be accessed and to dynamically update a control signal to cause the communication of the clock signal to be dynamically switched between a fixed clock frequency and a spread spectrum clock frequency based at least in part on the indication of communication to the next device. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes: a processing circuit to execute instructions; and a host controller coupled to the processing circuit to perform a key exchange with a second device to couple to the apparatus via a bus to which a plurality of devices may be coupled, and in response to a successful completion of the key exchange, enable secure communication with the second device. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes an input/output (I/O) circuit to communicate information at a selected voltage via an interconnect to which a plurality of devices may be coupled, and a host controller to couple to the interconnect. The host controller may include a supply voltage policy control circuit to initiate a supply voltage policy exchange with a first device to obtain a first supply voltage capability of the first device and to cause the I/O circuit and the first device to be configured to communicate via the interconnect at a first supply voltage based on the first supply voltage capability. Other embodiments are described and claimed.

Abstract: The disclosed embodiments relate to methods, systems and apparatus for dynamic temperature aware functional safety. The disclosed embodiments provide adaptive techniques to track extended dynamic temperature range of a System-on-Chip (SOC) and automatically tune critical IP components of the SOC so that system can operate reliably even at high temperatures. The disclosed embodiments relax the overdesign of the SOC components by reusing existing components such as a ring oscillator to determine temperature at different regions of the SOC. In one embodiment, the disclosed principles use a Calibrated Ring Oscillator (CRO) temperature sensors. The CRO-based temperature sensors provide fast temperature measurement suitable for detecting dynamic temperature ranges and temperature rate of change. The CROs are existing on the SOC and do not require addition of additional sensors.

Abstract: Embodiments include apparatuses, methods, and systems for testing that include a programmable tester coupled to a master-slave device network having a master device and at least one slave device. The programmable tester is to receive a configuration mode from a host to test a function of a selected device of the master device or the at least one slave device. The configuration mode is to indicate that the programmable tester is to be configured to operate in a slave mode or in a master mode. The programmable tester is further configured according to the configuration mode, to send test data to test the function of the selected device, determine a test result based on response data by the selected device to the test data, and indicate whether the selected device is in a faulty state with respect to the function. Other embodiments may also be described and claimed.

Abstract: Methods and apparatus relating to functional safety clocking framework for real time systems are described. In an embodiment, clock monitoring logic circuitry monitors a plurality of clock signals. Safety island logic circuitry receives an error status signal from the clock monitoring logic circuitry based at least in part on a determination of whether an error exists for at least one of the plurality of clock signals. Safety logic circuitry to receive an interrupt signal from the safety island logic circuitry in response to a determination that the error status signal indicates existence of an error for at least one of the plurality of clock signals. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to functional safety critical audio system for autonomous and industrial applications are described. In an embodiment, safety island logic circuitry transmits an enable signal to cause initiation of a functional safety test for an audio component in a vehicle. Audio processing logic circuitry receives the enable signal and causes activation of power amplifier logic circuitry, in response to the enable signal, to drive the audio component in accordance with an audio alert test signal. The audio component includes a Parametric Acoustic Array (PAA) transducer. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, an apparatus includes: at least one processing circuit; at least one array associated with the at least one processing circuit; a power controller to manage power consumption of the apparatus; and a fabric bridge coupled to the power controller. The fabric bridge and power controller may be configured to implement a handshaking protocol to enable the fabric bridge to receive data from the at least one array via a sideband communication path and send the data to a system memory coupled to the apparatus via a primary communication path, prior to entry of the apparatus into a first low power state. Other embodiments are described and claimed.

Abstract: In one embodiment, a host controller includes: a first input/output (I/O) buffer to couple to a first communication line of an interconnect; a second I/O buffer to couple to a second communication line of the interconnect; and a device group selection circuit to dynamically cause the first communication line to communicate a clock signal to a first device group including one or more first devices to couple to the interconnect and dynamically cause the second communication line to communicate a data signal to the first device group when a communication is to be addressed to at least one of the one or more first devices of the first device group, such that the communication is transparent to at least another device group to couple to the interconnect. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus includes: an accelerator to execute instructions; an accelerator request decoder coupled to the accelerator to perform a first level decode of requests from the accelerator and direct the requests based on the first level decode, the accelerator request decoder including a memory map to identify a first address range associated with a local memory and a second address range associated with a system memory; and a non-coherent request router coupled to the accelerator request decoder to receive non-coherent requests from the accelerator request decoder and perform a second level decode of the non-coherent requests, the non-coherent request router to route first non-coherent requests to a sideband router of the first die and to direct second non-coherent requests to a computing die. Other embodiments are described and claimed.

Abstract: An apparatus is provided which comprises: a first circuitry to track a spread spectrum of a differential signal according to sampled data; and a second circuitry to adjust phase of a clock according to the spread spectrum, wherein the clock is used for sampling the differential signal.

Abstract: Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.

Abstract: In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

Abstract: Apparatus for managing high speed Universal Serial Bus 2.0 (USB2) communications is presented. The apparatus may include a combination differential difference detector to receive first and second input signals, the combination differential difference detector to, in a first mode: sense a first voltage difference between the first and second input signals and output a squelch signal when the first voltage difference is less than or equal to a pre-defined value. The combination differential difference detector is to, in a second mode, sense a second voltage difference between the first and second input signals and output a disconnect signal when the second voltage difference is greater than or equal to a pre-defined value. Related methods may also be disclosed.

Abstract: An apparatus is provided which comprises: a receiver to receive a differential clock; a delay locked loop (DLL) coupled to the receiver; a first phase interpolator (PI) coupled to the DLL, the first PI to provide a first clock phase; a second PI coupled to the DLL, wherein the second PI is to provide a second or third clock phase; circuitry to adjust the first and second PIs according to the first clock phase, and the second or third clock phase.

Abstract: In one embodiment, an apparatus includes a host controller to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto a first line of the interconnect; a second driver to drive a clock signal onto a second line of the interconnect; and a mode control circuit to cause the second driver to drive the clock signal onto the second line of the interconnect in a first mode and to cause the first driver and the second driver to drive differential information onto the first line and the second line of the interconnect in a second mode. Other embodiments are described and claimed.

Abstract: A configuration interface bus may be coupled to components of a physical layer (PHY) device. A configuration controller may be coupled with the configuration interface bus and may receive an input signal representing a power state of the PHY device. The configuration controller may further identify a set of instructions that correspond to the input signal and may transmit configuration data via the configuration interface bus to one or more of the components of the PHY device in response to an execution of the set of instructions. The operation of the one or more components of the PHY device may be based on the configuration data.

Abstract: In one embodiment, an apparatus includes: a first controller to couple to an interconnect to which a plurality of devices may be coupled, the first controller to communicate first information via the interconnect according to the native communication protocol; a first transceiver to drive the first information onto a first line of the interconnect; a second transceiver to drive a clock signal onto a second line of the interconnect; and a second controller to communicate second information via the interconnect. In an embodiment, the native communication protocol is a single-ended communication protocol and the second controller is to communicate the second information differentially via the interconnect. Other embodiments are described and claimed.

Abstract: A microelectronic assembly may include a first microelectronic device, a second microelectronic device, a first signal link, a second signal link, and a first power connection. The first microelectronic device may include a first interface powered at a first voltage. The second microelectronic device may include a second interface powered at a second voltage. The first signal link may supply a first signal at the first voltage from the first interface to the second interface. The second signal link may supply a second signal at the second voltage from the second interface to the first interface. The first power connection may supply a first reference signal at the first voltage from the first interface to the second interface.