Patents by Inventor An-Cheng Huang

An-Cheng Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955370
    Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Cyuan Lu, Ting-Gang Chen, Sung-En Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui, Tai-Chun Huang, Chieh-Ping Wang
  • Patent number: 11953738
    Abstract: The present invention discloses a display including a display panel and a light redirecting film disposed on the viewing side of the display panel. The light redirecting film comprises a light redistribution layer, and a light guide layer disposed on the light redistribution layer. The light redistribution layer includes a plurality of strip-shaped micro prisms extending along a first direction and arranged at intervals and a plurality of diffraction gratings arranged at the bottom of the intervals between the adjacent strip-shaped micro prisms, wherein each of the strip-shaped micro prisms has at least one inclined light-guide surface, and the bottom of each interval has at least one set of diffraction gratings, and the light guide layer is in contact with the strip-shaped micro prisms and the diffraction gratings.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: April 9, 2024
    Assignee: BenQ Materials Corporation
    Inventors: Cyun-Tai Hong, Yu-Da Chen, Hsu-Cheng Cheng, Meng-Chieh Wu, Chuen-Nan Shen, Kuo-Jung Huang, Wei-Jyun Chen, Yu-Jyuan Dai
  • Patent number: 11952420
    Abstract: Provided herein are antibodies, or antigen-binding portions thereof, that specifically bind and inhibit TREM-1 signaling, wherein the antibodies do not bind to one or more Fc?Rs and do not induce the myeloid cells to produce inflammatory cytokines. Also provided are uses of such antibodies, or antigen-binding portions thereof, in therapeutic applications, such as treatment of autoimmune diseases.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: April 9, 2024
    Assignee: BRISTOL-MYERS SQUIBB COMPANY
    Inventors: Achal Pashine, Michael L Gosselin, Aaron P. Yamniuk, Derek A. Holmes, Guodong Chen, Priyanka Apurva Madia, Richard Yu-Cheng Huang, Stephen Michael Carl
  • Patent number: 11955191
    Abstract: A memory device and a method of operating a memory device are disclosed. In one aspect, the memory device includes a plurality of non-volatile memory cells, each of the plurality of non-volatile memory cells is operatively coupled to a word line, a gate control line, and a bit line. Each of the plurality of non-volatile memory cells comprises a first transistor, a second transistor, a first diode-connected transistor, and a capacitor. The first transistor, second transistor, first diode-connected transistor are coupled in series, with the capacitor having a first terminal connected to a common node between the first diode-connected transistor and the second transistor.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Perng-Fei Yuh, Tung-Cheng Chang, Gu-Huan Li, Chia-En Huang, Chun-Ying Lee, Yih Wang
  • Patent number: 11955507
    Abstract: A light-emitting device, including a first type semiconductor layer, a patterned insulating layer, a light-emitting layer, and a second type semiconductor layer, is provided. The patterned insulating layer covers the first type semiconductor layer and has a plurality of insulating openings. The insulating openings are separated from each other. The light-emitting layer is located in the plurality of insulating openings and covers a portion of the first type semiconductor layer. The second type semiconductor layer is located on the light-emitting layer.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: April 9, 2024
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Hsin-Hung Li, Wei-Syun Wang, Chih-Chiang Chen, Yu-Cheng Shih, Cheng-Chan Wang, Chia-Hsin Chung, Ming-Jui Wang, Sheng-Ming Huang
  • Publication number: 20240113288
    Abstract: This application relates to a negative electrode plate, a secondary battery and apparatus thereof. The secondary battery of the present application comprises a negative electrode plate, the negative electrode plate comprises a composite current collector and a negative electrode active material layer disposed on at least one surface of the composite current collector, the negative electrode active material layer comprises a silicon-based active material, the silicon-based active material accounts for 0.5 wt % to 50 wt % of total mass of the negative electrode active material layer, and the composite current collector comprises a polymer support layer and a metal conductive layer disposed on at least one surface of the polymer support layer. The secondary battery and the negative electrode plate achieve good coordination between the current collector and the negative electrode active material layer.
    Type: Application
    Filed: November 30, 2023
    Publication date: April 4, 2024
    Applicant: Contemporary Amperex Technology Co., Limited
    Inventors: Cheng LI, Qisen HUANG, Xin LIU, Changliang SHENG, Shiwen WANG, Xianghui LIU, Jia PENG, Mingling LI, Chengdu LIANG
  • Publication number: 20240109230
    Abstract: A manufacturing method of housing structure of electronic device is provided. The manufacturing method includes stacking a first structural layer, a painting layer, and a second structural layer, wherein the painting layer is located between the first and the second structural layers. The layer stacked after the painting layer washes and squeezes at least a portion of the flowing painting layer to form a random texture pattern.
    Type: Application
    Filed: May 16, 2023
    Publication date: April 4, 2024
    Applicants: Acer Incorporated, Nan Pao New Materials (Huaian) Co., Ltd.
    Inventors: Pin-Chueh Lin, Wen-Chieh Tai, Cheng-Nan Ling, Chang-Huang Huang
  • Publication number: 20240114614
    Abstract: Disclosed is a thermal conduction-electrical conduction isolated circuit board with a ceramic substrate and a power transistor embedded, mainly comprising: a dielectric material layer, a heat-dissipating ceramic block, a securing portion, a stepped metal electrode layer, a power transistor, and a dielectric material packaging, wherein a via hole is formed in the dielectric material layer, the heat-dissipating ceramic block is correspondingly embedded in the via hole, the heat-dissipating ceramic block has a thermal conductivity higher than that of the dielectric material layer and a thickness less than that of the dielectric material layer, the stepped metal electrode layer conducts electricity and heat for the power transistor, the dielectric material packaging is configured to partially expose the source connecting pin, drain connecting pin, and gate connecting pin of the encapsulated stepped metal electrode layer.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: HO-CHIEH YU, CHEN-CHENG-LUNG LIAO, CHUN-YU LIN, JASON AN CHENG HUANG, CHIH-CHUAN LIANG, KUN-TZU CHEN, NAI-HIS HU, LIANG-YO CHEN
  • Publication number: 20240109995
    Abstract: A preparation method of solvent-free self-emulsifying water-soluble chlorinated polypropylene is provided. By uniformly mixing chlorinated polypropylene, an acrylic acid/ester mixture and a cosolvent, initiating the chlorinated polypropylene to generate free radicals by using an initiator, further initiating free radical polymerization of the acrylic acid/ester mixture, then adding an isocyanate-terminal carboxyl hyperbranched polyester adduct, reacting, then neutralizing with amine, emulsifying, and diluting with deionized water, the solvent-free self-emulsifying water-soluble chlorinated polypropylene with a solid content of 30-45% may be obtained. The process of the present invention is simple, and easy to industrialize, and the product has the advantages of low VOC content, no organic solvent, water dilution, excellent stability, etc., and is expected to be widely used in the fields of water-soluble paints, surface modification of non-polar or low-polar plastics and the like.
    Type: Application
    Filed: November 17, 2023
    Publication date: April 4, 2024
    Applicants: WUHAN HYPERBRANCHED POLYMERS SCIENCE & TECHNOLOGY CO., LTD., HUBEI HYPERBRANCHED NEW MATERIALS SCIENCE & TECHNOLOGY CO., LTD.
    Inventors: Sufang CHEN, Sunmeng HUANG, Yangjie LUO, Cheng XU
  • Publication number: 20240113195
    Abstract: Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a dielectric wall adjacent to the first nanostructures. The semiconductor structure also includes a first liner layer between the first nanostructures and the dielectric wall, and the first liner layer is in direct contact with the dielectric wall. The semiconductor structure also includes a gate structure surrounding the first nanostructures, and the first liner layer is in direct contact with a portion of the gate structure.
    Type: Application
    Filed: February 22, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jia-Ni YU, Lung-Kun CHU, Chun-Fu LU, Chung-Wei HSU, Mao-Lin HUANG, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20240110976
    Abstract: An electronic device and a method for performing clock gating in the electronic device are provided. The electronic device includes at least one function circuit, a device under test (DUT) circuit and at least one gating circuit. The function circuit is configured to operate according to at least one primary clock, and the DUT circuit is configured to operate according to at least one secondary clock. In addition, the clock gating circuit is configured to control whether to enable the primary clock according to at least one primary enable signal, and control whether to enable the secondary clock according to the primary enable signal and a secondary enable signal.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 4, 2024
    Applicant: Realtek Semiconductor Corp.
    Inventors: Ching-Feng Huang, Yu-Cheng Lo
  • Patent number: 11946733
    Abstract: An image rendering device and an image rendering method are disclosed. For the elements of the image rendering device, a first sensor and a second sensor are configured to sense a target object in a two-dimensional (2D) mode and three-dimensional (3D) mode to generate a first surface-color-signal, a first 3D-depth-signal, a second surface-color-signal and a second 3D-depth-signal respectively. An IR projector is configured to generate an IR-dot-pattern. A processor is configured to control the IR projector to project the IR-dot-pattern on the target object in the 3D mode, and configured to process the first surface-color-signal, the second surface-color-signal, the first 3D-depth-signal and the second 3D-depth-signal to obtain a color 3D model of the target object.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: April 2, 2024
    Assignee: EYS3D MICROELECTRONICS CO.
    Inventors: Kuan-Cheng Chung, Tsung-Yi Huang, Shi-Fan Chang
  • Patent number: 11948796
    Abstract: One or more embodiments described herein relate to selective methods for fabricating devices and structures. In these embodiments, the devices are exposed inside the process volume of a process chamber. Precursor gases are flowed in the process volume at certain flow ratios and at certain process conditions. The process conditions described herein result in selective epitaxial layer growth on the {100} planes of the crystal planes of the devices, which corresponds to the top of each of the fins. Additionally, the process conditions result in selective etching of the {110} plane of the crystal planes, which corresponds to the sidewalls of each of the fins. As such, the methods described herein provide a way to grow or etch epitaxial films at different crystal planes. Furthermore, the methods described herein allow for simultaneous epitaxial film growth and etch to occur on the different crystal planes.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: April 2, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Yi-Chiau Huang, Chen-Ying Wu, Abhishek Dube, Chia Cheng Chin, Saurabh Chopra
  • Patent number: 11947150
    Abstract: A backlit-module-embedded illuminated keyswitch structure includes a baseplate, a mask film disposed below the baseplate and having a first coating configured to substantially reflect a light, a light guide sheet disposed at one side of the mask film and having a light source hole, a reflective layer disposed at one side of the light guide sheet opposite to the mask film and having an opening communicating with the light source hole, a top glue configured to connect the mask film and the light guide sheet around the light source hole, and a bottom glue configured to connect the light guide sheet and the reflective layer around the light source hole. The first coating covers the light source hole. In a stacked direction of the mask film, the light guide sheet, and the reflective layer, at least one of the top glue and the bottom glue overlaps the first coating.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: April 2, 2024
    Assignee: DARFON ELECTRONICS CORP.
    Inventors: Heng-Yi Huang, Hsin-Cheng Ho, Po-Yueh Chou
  • Patent number: 11948581
    Abstract: A smart interpreter engine is provided. The smart interpreter engine includes a speech to text converter, a natural language processing module and a translator. The speech to text converter is utilized for converting speech data corresponding to a first language into text data corresponding to the first language. The natural language processing module is utilized for converting the text data corresponding to the first language into glossary text data corresponding to the first language according to a game software. The translator is utilized for converting the glossary text data corresponding to the first language into text data corresponding to a second language.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: April 2, 2024
    Assignee: ACER INCORPORATED
    Inventors: Gianna Tseng, Shih-Cheng Huang, Shang-Yao Lin, Szu-Ting Chou
  • Patent number: 11948987
    Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.
    Type: Grant
    Filed: September 9, 2020
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11948016
    Abstract: Embodiments of the present invention relate to a method, system and computer program product for application programming interface (API) management. According to the method, in response to a first response from an API provider indicating a failure of a first API request initiated by an API requestor, a second API request is generated at least based on the first API request. The second API request is transmitted to the API provider. A second response to the second API request is received from the API provider. A third response is provided to the API requestor based on the second response.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: April 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Yun Fei Yuan, Qun Pan, Zhun Huang, Xiang Juan Meng, Cheng Fang Wang
  • Patent number: 11949051
    Abstract: A wavelength conversion member includes a substrate, a phosphor layer, and a ventilated blade. The substrate is configured to rotate based on an axis. The phosphor layer is disposed on the substrate. The ventilated blade is disposed on the substrate and has a pore density between 10 ppi and 500 ppi or a volume porosity between 5% and 95%.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: April 2, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yen-I Chou, Jih-Chi Li, Wen-Cheng Huang
  • Publication number: 20240105546
    Abstract: A module device on a first substrate includes a power module, a housing, a pair of locking structures. The housing covers the power module. The locking structures are installed on a pair of opposite sides of the housing, and the locking structure includes a main body, a locking ring, a pair of ribs and anchoring portions. The locking ring extends from a side toward an inner side of the main body, and is a double-ring structure, which includes an inner and an outer ring. A first side of the outer ring is connected to the main body, a second side of the outer ring is connected to the inner ring. The ribs extend along a normal direction of the top surface of the main body. The anchoring portions are disposed at the end of the ribs, and an extending direction is perpendicular to an extending direction of the rib.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 28, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Ji-Yuan Syu, Yuan-Cheng Huang, Yu-Chih Wang
  • Publication number: 20240102959
    Abstract: An IC structure includes a biologically sensitive field-effect transistor (BioBET) in a semiconductor substrate, and a dielectric layer over a backside surface of the semiconductor substrate. The dielectric layer has a sensing well extending through the dielectric layer to a channel region of the BioFET. The IC structure further includes a biosensing film, a plurality of fluid channel walls, and a first heater. The biosensing film lines the sensing well in the dielectric layer. The fluid channel walls are over the biosensing film and define a fluid containment region over the sensing well of the dielectric layer. The first heater is in the semiconductor substrate. The first heater has at least a portion overlapping with the fluid containment region.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 28, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Tsun CHEN, Yi-Hsing HSIAO, Jui-Cheng HUANG, Yu-Jie HUANG