Abstract: A cover plate of a cylindrical battery and the cylindrical battery are provided by the present application. The cover plate of the cylindrical battery includes a pole column. A bottom of the pole column is connected with a current collecting plate. The pole column is sleeved with a sealing ring. A first insulating element and a cover slip are sequentially sleeved on an outside of the sealing ring along a vertical direction. The first insulating element insulates the current collecting plate from the cover slip.

Abstract: An electronic device and a method for detecting abnormal device operation are provided. The method includes: obtaining multiple action events of a movable input device, and each action event including a relative coordinate and a time stamp of the movable input device; generating multiple absolute coordinates based on the relative coordinate of each action event; estimating multiple speed vectors based on the absolute coordinates and the time stamp of each action event; estimating multiple acceleration vectors based on the speed vectors and the time stamp of each action event; and estimating a probability of abnormal operation based on the speed vectors and the acceleration vectors.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first source/drain epitaxial feature, a second source/drain epitaxial feature disposed adjacent the first source/drain epitaxial feature, a first dielectric layer disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a first dielectric spacer disposed under the first dielectric layer, and a second dielectric layer disposed under the first dielectric layer and in contact with the first dielectric spacer. The second dielectric layer and the first dielectric spacer include different materials.

Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.

Abstract: A biosensor system includes an array of biosensors with a plurality of electrodes situated proximate the biosensor. A controller is configured to selectively energize the plurality of electrodes to generate a DEP force to selectively position a test sample relative to the array of biosensors.

Abstract: The present disclosure provides a semiconductor structure, including a substrate having a front surface, a first semiconductor layer proximal to the front surface, a second semiconductor layer over the first semiconductor layer, a gate having a portion between the first semiconductor layer and the second semiconductor layer, a spacer between the first semiconductor layer and the second semiconductor layer, contacting the gate, and a source/drain (S/D) region, wherein the S/D region is in direct contact with a bottom surface of the second semiconductor layer, and the spacer has an upper surface interfacing with the second semiconductor layer, the upper surface including a first section proximal to the S/D region, a second section proximal to the gate, and a third section between the first section and the second section.

Abstract: A mounting frame for being mounted with either one of first and second screwdrivers, includes a main frame, a mounting seat, and first and second mounting plates. The mounting seat has a plate attachment hole set. The first mounting plate has a first seat attachment hole set operable to be connected to the plate attachment hole set, and a first driver attachment hole set for the first screwdriver to be attached thereto. The second mounting plate has a second seat attachment hole set operable to be connected to the plate attachment hole set, and a second driver attachment hole set for the second screwdriver to be attached thereto.

Abstract: A method for preparing antibacterial stainless steel by surface alloying includes the steps of coating an infiltration promoter layer on a stainless steel surface, coating an antibacterial metal layer on a surface of the infiltration promoter layer, and performing heat treatment of the stainless steel to diffuse an antibacterial metal into the stainless steel. This method can be applied to various types of stainless steel, and the antibacterial metal can be diffused and quenched into the stainless steel, such that the finally formed surface of the stainless steel has an antibacterial alloy layer with a specific thickness to provide better corrosion resistance and antibacterial ability without changing the advantages and properties of the antibacterial metal or stainless steel substrate, and the thickness and concentration of the antibacterial metal layer, and the parameters for heat treatment can be adjusted to control the chemical composition and thickness of the antibacterial alloy layer.

Abstract: A method for treating wastewater containing ertriazole compounds is provided. Hypochlorous acid (HOCl) having a neutral to slightly acidic pH value is added to the wastewater containing triazole compounds for reaction, thereby effectively reacting more than 90% of triazole compounds.

Abstract: A foldable electronic apparatus is provided and includes a base unit and a display unit. The display unit includes a main panel body having a first side and a bottom side substantially perpendicular to each other, and the bottom side is connected to the base unit; a first folding module disposed on the first side; a first side panel body disposed on the first folding module, and the first side panel body is able to transform between a first unfolded state and a first folded state relative to the main panel body with the first folding module as an axis; and a flexible screen disposed on the main panel body, the first folding module and the first side panel body, and the flexible screen includes a first bendable area corresponding to the first folding module.

Abstract: Some embodiment structures and methods are described. A structure includes an integrated circuit die at least laterally encapsulated by an encapsulant, and a redistribution structure on the integrated circuit die and encapsulant. The redistribution structure is electrically coupled to the integrated circuit die. The redistribution structure includes a first dielectric layer on at least the encapsulant, a metallization pattern on the first dielectric layer, a metal oxide layered structure on the metallization pattern, and a second dielectric layer on the first dielectric layer and the metallization pattern. The metal oxide layered structure includes a metal oxide layer having a ratio of metal atoms to oxygen atoms that is substantially 1:1, and a thickness of the metal oxide layered structure is at least 50 ?. The second dielectric layer is a photo-sensitive material. The metal oxide layered structure is disposed between the metallization pattern and the second dielectric layer.

Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a first source/drain region disposed in a PFET region and a second source/drain region disposed in an NFET region. The second source/drain region comprises a dipole region. The structure further includes a first silicide layer disposed on and in contact with the first source/drain region, a second silicide layer disposed on and in contact with the first silicide layer, and a third silicide layer disposed on and in contact with the dipole region of the second source/drain region. The first, second, and third silicide layers include different materials. The structure further includes a first conductive feature disposed over the first source/drain region, a second conductive feature disposed over the second source/drain region, and an interconnect structure disposed on the first and second conductive features.

Abstract: A seismic quantitative prediction method for shale total organic carbon (TOC) based on sensitive parameter volumes is as follows. A target stratum for a TOC content to be measured is determined, logging curves with high correlations with TOC contents are analyzed, the logging curves are found as sensitive parameters; sample data are constructed using the sensitive parameters; a radial basis function (RBF) neural network is trained with the sample data as an input and the TOC content at a depth corresponding to the sample data as an output to obtain a RBF neural network prediction model; sensitive parameter volumes are obtained by using the sensitive parameters and post stack three-dimension seismic data to invert; prediction samples are constructed using the sensitive parameter volumes; the predicted samples are input to the RBF neural network prediction model to calculate corresponding TOC values, thereby the TOC content of the target stratum is predicted.

Abstract: A turbine of a power generating system includes a rotary shaft, blades, stoppers and elastic members. Each of the blades includes a connecting side and an active side opposite to the connecting side, and the blades are disposed on the rotary shaft at intervals by a predetermined distance, in which the blades are pivotally connected to the rotary shaft through the connecting sides. The stoppers respectively correspond to the blades and are disposed over the rotary shaft for limiting expansion angles of the blades. Each of the elastic members includes a fixed end and a moving end opposite to the fixed end, and the fixed ends attach to the rotary shaft, and the moving ends respectively attach to the blades. Each of the blades pivots between an expanded position and a closed position.

Abstract: In some examples, a device can include an antenna to emit waves in a radiation pattern having a first beamwidth, a directional radiation control device located in a path of the waves, where the directional radiation control device is to receive the waves from the antenna and is shaped to cause the waves to be directed in a different radiation pattern having a second beamwidth that is larger than the first beamwidth.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.

Abstract: A device structure according to the present disclosure may include a first die having a first substrate and a first interconnect structure, a second die having a second substrate and a second interconnect structure, and a third die having a third interconnect structure and a third substrate. The first interconnect structure is bonded to the second substrate via a first plurality of bonding layers. The second interconnect structure is bonded to the third interconnect structure via a second plurality of bonding layers. The third substrate includes a plurality of photodiodes and a first transistor. The second die includes a second transistor having a source connected to a drain of the first transistor, a third transistor having a gate connected to drain of the first transistor and the source of the second transistor, and a fourth transistor having a drain connected to the source of the third transistor.

Abstract: The present invention discloses an integrated choke assembly comprising: a base having a main body structure, a first protruding part and a second protruding part. A first choke has a first magnetic core and a first winding, wherein the first protruding part is arranged through the first opening of the first magnetic core so that the first choke is arranged on the upper surface of the main body structure, and the first winding is wound on the first magnetic core. A second choke has a second magnetic core and a second winding, wherein the second protruding part is arranged through the second opening of the second magnetic core so that the second choke is arranged on the lower surface of the main body structure, and the second winding is wound on the second magnetic core.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.