Abstract: The present disclosure provides a wafer. The wafer includes a die, a scribe line adjacent to the die, and a test circuit adjacent to the scribe line. The test circuit includes a first switch configured to simultaneously couple a first DUT of a first set of DUTs arranged in a first column and a second DUT of a second set of DUTs arranged in a second column to a signal supply node. The test circuit includes a second switch configured to simultaneously couple the first DUT and the second DUT to a signal receive node. The second switch has a node directly coupled to the first DUT, the second DUT, and the first switch. There is no switch connected between the first DUT and the second DUT.

Abstract: A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.

Abstract: A method of forming a gas spacer in a semiconductor device and a semiconductor device including the same are disclosed. In accordance with an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer on sidewalls of the first gate spacer; removing the second gate spacer using an etching process to form a first opening, the etching process being performed at a temperature less than 0° C., the etching process using an etching solution including hydrogen fluoride; and depositing a dielectric layer over the first gate spacer and the gate stack, the dielectric layer sealing a gas spacer in the first opening.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a channel layer extending along a vertical direction, and a top S/D structure formed on the channel layer. The semiconductor structure also includes a bottom S/D structure formed below the channel layer, and a gate structure adjacent to the channel layer. The channel layer is surrounded by the gate structure. The semiconductor structure includes a top inner spacer layer formed on the gate structure, and a top surface of the channel layer is higher than a bottom surface of the top inner spacer layer.

Abstract: A contact structure, contact pad layout and structure, mask combination and manufacturing method thereof is provided in the present invention. Through the connection of tops of at least two contact plugs in the boundary of core region, an integrated contact with larger cross-sectional area is formed in the boundary of core region. Accordingly, the process of forming electronic components on the contact structure in the boundary of core region may be provided with sufficient process window to increase the size of electronic components in the boundary, lower contact resistance, and the electronic component with increased size in the boundary buffer the density difference of circuit patterns between the core region and the peripheral region, thereby improving optical proximity effect and ensuring the uniformity of electronic components on the contact plugs inside the boundary of core region, and avoiding the collapse of electronic components on the contact plug in the boundary.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a magnetic element over the substrate. The semiconductor device structure also includes an isolation layer extending exceeding edges the magnetic element. The isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding the edges of the magnetic element.

Abstract: The present disclosure provides a GGNMOS transistor structure, an ESD protection device, and an ESD protection circuit. The GGNMOS transistor structure can increase a capability of the ESD protection device to discharge an ESD current per unit size under the action of a P-N-P-N parasitic thyristor formed by an N-potential well, a P-type heavily doped region, and an N-type heavily doped region; the GGNMOS transistor structure can limit a transient peak current of ESD under the action of an equivalent resistor formed by an N-potential well, so that respective GGNMOS transistors of the ESD protection device can conduct uniformly, improving the reliability of the ESD protection circuit.

Abstract: Embodiments of the present disclosure provide a method and an apparatus for video processing, and a storage medium and an electronic apparatus. The method comprises: determining a neural network loop filtering enabled flag of a reconstructed video unit; setting, based on the neural network loop filtering enabled flag, an adaptive loop filtering enabled flag for the reconstructed video unit; and signaling at least one type of the following information: filter information related to neural network loop filter of the reconstructed video unit, and filter information related to adaptive loop filter of the reconstructed video unit.

Abstract: A first lock assembly comprises a first alignment component operatively rotationally connected with the first rotatable component and a second lock assembly comprises a second alignment component operatively rotationally connected with the second rotatable component that will engage with one another upon moving the first door proximate to the second door, at least one of the first and second alignment components having a predetermined rotational orientation for engagement with the other of the first and second alignment components, the first and second alignment components each including interacting surfaces that during engagement with one another rotationally align the first and second alignment components with one another to create an effective rotational translational connection from the first lock assembly to the second lock assembly, whereby user initiated rotation of either the first or second rotatable component can cause locking or unlocking of the lockbolt or latch in one of or both the first and sec

Abstract: A nonaqueous electrochemical battery is provided. The battery comprises a housing containing an interior space extending to an open end, as well as positive electrode, negative electrode, separator, and electrolyte disposed within the interior space of the housing. A sealing member is disposed adjacent to the open end of the housing, wherein the sealing member comprises a polymer composition that contains a polyarylene sulfide and a bifunctional polymer that contains an epoxide functional group and a (meth)acrylate functional group. The polymer composition has an epoxy content of from about 0.3 to about 2 parts by weight per 100 parts by weight of polyarylene sulfides in the polymer composition.

Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.

Abstract: A second metal structure such as a metal plug is formed over a first metal structure, such as a metal line, by causing metal material from the first metal structure to migrate into an opening in a dielectric layer over the first metal structure. The metal material, which may be copper, is of a type that undergoes a reduction in density as it oxidizes. Migration is induced using gases that alternately oxidize and reduce the metal material. Over many cycles, the metal material migrates into the opening. In some embodiments, the migrated metal material partially fills the opening. In some embodiments, the migrated metal material completely fills the opening.

Abstract: The present disclosure discloses a common source transistor apparatus. The common source transistor unit includes a diffusion area, poly-silicon gates and a source/bulk ring. The diffusion area includes source/bulk areas and drain areas. Each of the poly-silicon gates traverses the diffusion areas between one of the source/bulk areas and one of the drain areas and includes a low-voltage gate part, a first high-voltage gate part and a second high-voltage gate part. The low-voltage gate part includes 2N low-voltage poly-silicon gates. Each of the first and the second high-voltage gate parts is disposed at a side of the low-voltage gate part having one of the source/bulk areas disposed therebetween and includes N+1 high-voltage poly-silicon gates. The source/bulk ring surrounds the diffusion and the poly-silicon gates and is coupled to the source/bulk area. An isolation ring surrounds the common source transistor unit. A substrate ring surrounds the isolation ring.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: An embodiment includes a method including forming an opening in a cut metal gate region of a metal gate structure of a semiconductor device, conformally depositing a first dielectric layer in the opening, conformally depositing a silicon layer over the first dielectric layer, performing an oxidation process on the silicon layer to form a first silicon oxide layer, filling the opening with a second silicon oxide layer, performing a chemical mechanical polishing on the second silicon oxide layer and the first dielectric layer to form a cut metal gate plug, the chemical mechanical polishing exposing the metal gate structure of the semiconductor device, and forming a first contact to a first portion of the metal gate structure and a second contact to a second portion of the metal gate structure, the first portion and the second portion of the metal gate structure being separated by the cut metal gate plug.

Abstract: A semiconductor device structure is provided. The structure includes a first gate electrode layer having at least three surfaces surrounded by a first intermixed layer, wherein the first intermixed layer comprises a first material and a second material. The structure also includes a second gate electrode layer disposed below and in contact with the first gate electrode layer, the second gate electrode layer having at least three surfaces surrounded by a second intermixed layer, wherein the second intermixed layer comprises the first material and a fifth material, wherein the first gate electrode layer and the second gate electrode layer are disposed between two adjacent dielectric spacers.

Abstract: Disclosed are a detection substrate and a detection device. The detection substrate includes: a plurality of photoelectric converters arranged in an array, where the photoelectric converter includes a plurality of film layers, an area of an overlapping region between electrode film layers forming an internal capacitor in the photoelectric converter is less than an area of the other film layer in the photoelectric converter; and a drive circuit electrically connected to the photoelectric converters.

Abstract: Provided are a cloud platform docking debugging method and apparatus, an electronic device, and a storage medium. The cloud platform docking debugging method includes steps below. According to debugging application information of a to-be-debugged application, a target Internet of Things device is determined from multiple candidate Internet of Things devices provided externally by the cloud platform, and the target Internet of Things device is allocated to the to-be-debugged application. Docking and debugging between the target Internet of Things device allocated to the to-be-debugged application and the to-be-debugged application on a development end side are controlled. The candidate Internet of Things device includes an Internet of Things device that is pre-built and accessed through the cloud platform and provides externally, as a public resource, a debugging service.

Abstract: A composite current collector includes a first metal layer, a second metal layer, and a first binding layer. The first metal layer includes a first body zone and a first tab zone. The first tab zone is located at an end of the first metal layer. The second metal layer includes a second body zone and a second tab zone. The second tab zone is located at an end of the second metal layer. The first body zone and the second body zone are connected through the first binding layer. The first tab zone has a thickness greater than thickness of the first body zone. The first tab zone extends toward the second tab zone.

Abstract: A testing apparatus includes a bottom tank comprising a plurality of coupling connectors; and a test shaft that includes a member that is rotatably connected to the plurality of coupling connectors, a plurality of perpendicular members that extend out from the member, and a plurality of device under test (DUT) members connected to the plurality of perpendicular members, wherein the plurality of DUT members each include a plurality of posts each to support a DUT.