Patents by Inventor An-Sung Wang

An-Sung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240161492
    Abstract: The present invention relates to an image collection sensor device, an unmanned counting edge computing system and method using the same, and more particularly, to an image collection sensor device capable of providing a high-precision unmanned counting service using a low-power wireless image collection sensor device operated by a battery by analyzing unmanned counting result data that counts the number of persons included in image data, determining image sensor parameters of the image data, and adjusting a collection cycle and collection image quality of image sensor data according to environmental changes in a sensing area.
    Type: Application
    Filed: November 14, 2023
    Publication date: May 16, 2024
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Ryangsoo KIM, Sung Chang KIM, Hark YOO, Geun Yong KIM, Jaein KIM, Chorwon KIM, Hee Do KIM, Ji Hyoung RYU, Byung-Hee SON, Kicheoul WANG, Giha YOON
  • Publication number: 20240154310
    Abstract: An electronic device is provided having an antenna that also functions as a display shield for a display of the device. The display shield can separate components for a display module from other electrical components of the electronic device. The display shield can be grounded to an enclosure of the device at least partially by one or more shield grounding clips, and configured to receive and/or transmit radio frequency waves.
    Type: Application
    Filed: March 12, 2021
    Publication date: May 9, 2024
    Inventors: Pei Li, Zheyu Wang, Sung Hoon Oh, Jiang Zhu
  • Publication number: 20240153673
    Abstract: A flat flame-retardant harness system includes: a conductor including a plurality of connection contacts, a first position provided with a connector and a second position provided with a temperature sensor, and a wiring pattern for electrically connecting the plurality of connection contacts and the second position to the first position; a lower non-combustible layer provided to contact a lower portion of the conductor, having a plurality of first bus bar coupling portions having first holes formed at positions corresponding to the plurality of connection contacts, and including a flame-retardant material; and an upper non-combustible layer provided to contact the upper portion of the conductor, having a plurality of second bus bar coupling portions having second holes formed at positions corresponding to the plurality of connection contacts, and including a flame-retardant material, wherein each connection contact contacts a bus bar by a first means, and thus is electrically connected.
    Type: Application
    Filed: March 10, 2022
    Publication date: May 9, 2024
    Inventors: Young Sung Wang, Jeonghoon Je, Gyusang Choi
  • Publication number: 20240143141
    Abstract: The present disclosure generally relates to underwater user interfaces.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Benjamin W. BYLENOK, Alan AN, Richard J. BLANCO, Andrew CHEN, Maxime CHEVRETON, Kyle B. CRUZ, Walton FONG, Ki Myung LEE, Sung Chang LEE, Cheng-I LIN, Kenneth H. MAHAN, Anya PRASITTHIPAYONG, Alyssa RAMDYAL, Eric SHI, Xuefeng WANG, Wei Guang WU
  • Publication number: 20240136223
    Abstract: A method to produce a layered substrate, which includes the steps of depositing a diffusion barrier layer on the substrate; depositing an underlayer comprising a Group 6 metal on the barrier layer; and depositing a ruthenium layer comprising ruthenium on the underlayer, to produce the layered substrate. A layered substrate is also disclosed.
    Type: Application
    Filed: October 20, 2022
    Publication date: April 25, 2024
    Inventors: Zhaoxuan WANG, Jianxin LEI, Wenting HOU, Sung-Kwan KANG, Anand Nilakantan IYER
  • Patent number: 11955370
    Abstract: A system and methods of forming a dielectric material within a trench are described herein. In an embodiment of the method, the method includes introducing a first precursor into a trench of a dielectric layer, such that portions of the first precursor react with the dielectric layer and attach on sidewalls of the trench. The method further includes partially etching portions of the first precursor on the sidewalls of the trench to expose upper portions of the sidewalls of the trench. The method further includes introducing a second precursor into the trench, such that portions of the second precursor react with the remaining portions of the first precursor to form the dielectric material at the bottom of the trench.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Bo-Cyuan Lu, Ting-Gang Chen, Sung-En Lin, Chunyao Wang, Yung-Cheng Lu, Chi On Chui, Tai-Chun Huang, Chieh-Ping Wang
  • Patent number: 11945772
    Abstract: A method including the step contacting an olefin, an alcohol, a metallosilicate catalyst and a solvent, wherein the solvent comprises structure (I): wherein R1 and R2 are each selected from the group consisting of an aryl group and an alkyl group with the proviso that at least one of R1 and R2 is an aryl group, further wherein n is 1-3.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 2, 2024
    Assignee: Dow Global Technologies LLC
    Inventors: Wen-Sheng Lee, Mingzhe Yu, Jing L. Houser, Sung-Yu Ku, Wanglin Yu, Stephen W. King, Paulami Majumdar, Le Wang
  • Publication number: 20240107473
    Abstract: A system is configured for reconfiguration of a Synchronization Signal Block (SSB) pattern. The system is configured for obtaining data including a configuration for a Synchronization Signal Block (SSB) transmission carrying a physical broadcast channel (PBCH), the configuration specifying, for an SSB of the configuration, resource elements (REs) allocated for transmitting a primary synchronization signal (PSS) to a user equipment (UE) and REs allocated for transmitting a secondary synchronization signal (SSS) to the UE. The system is configured for selecting a set of REs that are unused in the configuration for the SSB transmission, specifying a filling sequence for extending a synchronization signal or an SSB to the set of REs that are unused in the configuration of the SSB transmission, generating data including an enhanced configuration for the SSB transmission that includes the extended synchronization signal or the extended SSBs, and transmitting the SSB transmission using the enhanced configuration.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 28, 2024
    Inventors: Yihong Qi, Amir Aminzadeh Gohari, Amir Farajidana, Dan Zhang, Herbert R. Dawid, Idan Bar-Sade, Keith W. Saints, Onurcan Iscan, Ruoheng Liu, Sami M. Almalfouh, Sung Eun Lee, Tudor Ninacs, Wenshu Zhang, Yuanye Wang
  • Publication number: 20240107439
    Abstract: A system is configured for reconfiguration of a Synchronization Signal Block (SSB) pattern. The system is configured for obtaining data including a configuration for a Synchronization Signal Block (SSB) transmission carrying a physical broadcast channel (PBCH), the configuration specifying, for an SSB of the configuration, resource elements (REs) allocated for transmitting a primary synchronization signal (PSS) to a user equipment (UE) and REs allocated for transmitting a secondary synchronization signal (SSS) to the UE. The system is configured for selecting a set of REs that are unused in the configuration for the SSB transmission, specifying a filling sequence for extending a synchronization signal or an SSB to the set of REs that are unused in the configuration of the SSB transmission, generating data including an enhanced configuration for the SSB transmission that includes the extended synchronization signal or the extended SSBs, and transmitting the SSB transmission using the enhanced configuration.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 28, 2024
    Inventors: Yihong Qi, Amir Aminzadeh Gohari, Amir Farajidana, Dan Zhang, Herbert R. Dawid, Idan Bar-Sade, Keith W. Saints, Onurcan Iscan, Ruoheng Liu, Sami M. Almalfouh, Sung Eun Lee, Tudor Ninacs, Wenshu Zhang, Yuanye Wang
  • Publication number: 20240090213
    Abstract: A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 14, 2024
    Inventors: Jialiang WANG, Soonil LEE, Eswaranand VENKATASUBRAMANIAN, Chang Seok KANG, Sanjay G. KAMATH, Abhijit B. MALLICK, Srinivas GUGGILLA, Amy CHILD, Sung-Kwan KANG, Balasubramanian PRANATHARTHIHARAN
  • Publication number: 20240090190
    Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Jen CHEN, Wen-Hsi LEE, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
  • Patent number: 11916155
    Abstract: An optoelectronic package and a method for producing the optoelectronic package are provided. The optoelectronic package includes a carrier, a photonic device, a first encapsulant and a second encapsulant. The photonic device is disposed on the carrier. The first encapsulant covers the carrier and is disposed around the photonic device. The second encapsulant covers the first encapsulant and the photonic device. The first encapsulant has a topmost position and a bottommost position, and the topmost position is not higher than a surface of the photonic device.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: February 27, 2024
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORPORATION
    Inventors: Chien-Hsiu Huang, Bo-Jhih Chen, Kuo-Ming Chiu, Meng-Sung Chou, Wei-Te Cheng, Kai-Chieh Liang, Yun-Ta Chen, Yu-Han Wang
  • Publication number: 20240021548
    Abstract: A semiconductor device and method of manufacturing that includes a first etch stop layer and a second etch stop layer to prevent delamination and damage to underlying components. A first passivation layer and a second passivation layer are disposed on a substrate, with a metal pad exposed through the passivation layers and contacting a top metal component of the substrate. The first etch stop layer is then formed on the second passivation layer and the metal pad. A third passivation layer is then formed on the substrate with an opening to the metal pad, which is covered by the first etch stop layer. The second etch stop layer is then formed on the third passivation layer and in the opening on the second etch stop layer. A bottom metal film/conductive component is then formed on the second etch stop layer, photoresist is applied, and wet etching is performed. The metal pad is protected from damage caused by delamination of the second etch stop layer by the first etch stop layer.
    Type: Application
    Filed: July 13, 2022
    Publication date: January 18, 2024
    Inventors: Wei-Chun Liao, Guo-Zhou Huang, Huan-Kuan Su, Yu-Hong Pan, Wen Han Hung, Ling-Sung Wang
  • Publication number: 20230415204
    Abstract: A semiconductor cleaning tool is provided. The cleaning tool comprises a nozzle. The nozzle is connected with a first inlet to receive a carrier gas and a second inlet to receive one or more fluids. The nozzle comprises a gas passageway connected to the first inlet; and fluid passageway connected to the second inlet. The gas passageway comprises gas passage branches and the fluid passageway comprises fluid passage branches. The gas passage branches and the fluid passage branches are arranged interweavingly in the nozzle. Individual gas/fluid passage branches are controllable indecently and separately including a flow rate, a temperature, an on/off state, a type of fluid(s) or carrier gas, a time period, a supply mode, and/or any other aspects of spraying the fluid(s) and carrier gas through the individual gas passage branches and the individual fluid passage branches.
    Type: Application
    Filed: June 23, 2022
    Publication date: December 28, 2023
    Inventors: Hsu. Tung. Yen, Ling-Sung Wang, Chen-Chieh Chiang, P.H. Huang, C.L. Lin
  • Publication number: 20230411537
    Abstract: Semiconductor devices having increased capacitance without increased fin height or increased chip area are disclosed. Grooves are formed across a width of the fin(s) to increase the overlapping surface area with the gate terminal, in particular with a length of the groove being less than or equal to the fin width. Methods of forming such grooved fins and semiconductor capacitor devices are also described.
    Type: Application
    Filed: July 27, 2023
    Publication date: December 21, 2023
    Inventors: Cheng-You Tai, Sung-Hsin Yang, Tsung Jing Wu, Jung-Chi Jeng, Ling-Sung Wang, Ru-Shang Hsiao
  • Patent number: 11844205
    Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and for each active region, a portion of each of some but not all of the gate structures (gate extension) extending partially into the gap; and when viewing the gate structures as a group, the group having a notched profile relative to the second direction, where notches in the notched profile correspond to ones of the gate structures which are substantially free of extending into the gap.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: December 12, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Jen Chen, Wen-Hsi Lee, Ling-Sung Wang, I-Shan Huang, Chan-yu Hung
  • Publication number: 20230385508
    Abstract: A semiconductor structure includes first and second active regions extending in a first direction. The semiconductor structure further includes gate electrodes extending in a second direction perpendicular to the first direction. Each of the gate electrodes includes a first segment over at least one of the first active region or the second active region; a gate extension extending beyond each of the first active region and the second active region, wherein the gate extension has a uniform width in the first direction, and a conductive element, wherein a width of the conductive element in the first direction increases as a distance from the gate extension increases along an entirety of the conductive element in the second direction.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 30, 2023
    Inventors: Yu-Jen CHEN, Ling-Sung WANG, I-Shan HUANG, Chan-yu HUNG
  • Publication number: 20230369386
    Abstract: Semiconductor device structure and methods of forming the same are described. The structure includes a first dielectric layer including a first portion disposed over a source/drain region in an active region of a substrate and a modulation portion over an interlayer dielectric (ILD) in a resistor region of the substrate, the first portion of the first dielectric layer has a first composition, and the modulation portion of the first dielectric layer has a second composition different from the first composition. The structure further includes a resistor layer disposed on the modulation portion of the first dielectric layer in the resistor region and a second dielectric layer disposed over the first dielectric layer in the active region and over the resistor layer in the resistor region.
    Type: Application
    Filed: May 12, 2022
    Publication date: November 16, 2023
    Inventors: Hsueh-Han LU, Kun-Ei CHEN, Chen-Chieh CHIANG, Ling-Sung WANG, Jun-Nan NIAN
  • Patent number: D1018537
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: March 19, 2024
    Assignee: HTC CORPORATION
    Inventors: Shu-Kuen Chang, Natalia Amijo, Ian James McGillivray, Chin-Wei Chou, Yi-Shen Wang, Chih-Sung Fang, Hung-Yu Chen
  • Patent number: D1026910
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: May 14, 2024
    Assignee: HTC CORPORATION
    Inventors: Shu-Kuen Chang, Natalia Amijo, Ian James McGillivray, Chin-Wei Chou, Yi-Shen Wang, Chih-Sung Fang, Hung-Yu Chen